Uri C. Weiser

Publication Activity (10 Years)

Years Active: 1991-2023
Publications (10 Years): 26

Top Topics

Top Venues

IEEE Comput. Archit. Lett.

Publications

Samer Kurzum, Gil Shomron, Freddy Gabbay, Uri C. Weiser
Enhancing DNN Training Efficiency Via Dynamic Asymmetric Architecture. IEEE Comput. Archit. Lett. 22 (1) (2023)
Gil Shomron, Freddy Gabbay, Samer Kurzum, Uri C. Weiser
Post-Training Sparsity-Aware Quantization. NeurIPS (2021)
Gil Shomron, Freddy Gabbay, Samer Kurzum, Uri C. Weiser
Post-Training Sparsity-Aware Quantization. CoRR (2021)
Gil Shomron, Uri C. Weiser
Post-Training BatchNorm Recalibration. CoRR (2020)
Leeor Peled, Uri C. Weiser, Yoav Etsion
A Neural Network Prefetcher for Arbitrary Memory Access Patterns. ACM Trans. Archit. Code Optim. 16 (4) (2020)
Moran Shkolnik, Brian Chmiel, Ron Banner, Gil Shomron, Yury Nahshan, Alex M. Bronstein, Uri C. Weiser
Robust Quantization: One Model to Rule Them All. NeurIPS (2020)
Gil Shomron, Uri C. Weiser
Non-Blocking Simultaneous Multithreading: Embracing the Resiliency of Deep Neural Networks. CoRR (2020)
Gil Shomron, Uri C. Weiser
Non-Blocking Simultaneous Multithreading: Embracing the Resiliency of Deep Neural Networks. MICRO (2020)
Moran Shkolnik, Brian Chmiel, Ron Banner, Gil Shomron, Yury Nahshan, Alexander M. Bronstein, Uri C. Weiser
Robust Quantization: One Model to Rule Them All. CoRR (2020)
Leeor Peled, Uri C. Weiser, Yoav Etsion
Semantic prefetching using forecast slices. CoRR (2020)
Gil Shomron, Ron Banner, Moran Shkolnik, Uri C. Weiser
Thanks for Nothing: Predicting Zero-Valued Activations with Lightweight Convolutional Neural Networks. ECCV (10) (2020)
Gil Shomron, Ron Banner, Moran Shkolnik, Uri C. Weiser
Thanks for Nothing: Predicting Zero-Valued Activations with Lightweight Convolutional Neural Networks. CoRR (2019)
Gil Shomron, Tal Horowitz, Uri C. Weiser
SMT-SA: Simultaneous Multithreading in Systolic Arrays. IEEE Comput. Archit. Lett. 18 (2) (2019)
Gil Shomron, Uri C. Weiser
Spatial Correlation and Value Prediction in Convolutional Neural Networks. IEEE Comput. Archit. Lett. 18 (1) (2019)
Leeor Peled, Uri C. Weiser, Yoav Etsion
Towards Memory Prefetching with Neural Networks: Challenges and Insights. CoRR (2018)
Gil Shomron, Uri C. Weiser
Exploiting Spatial Correlation in Convolutional Neural Networks for Activation Value Prediction. CoRR (2018)
Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser
A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. CoRR (2017)
Uri C. Weiser
Insights from the 2016 Eckert-Mauchly Award Recipient. IEEE Micro 37 (3) (2017)
Leonid Yavits, Uri C. Weiser, Ran Ginosar
Resistive Address Decoder. IEEE Comput. Archit. Lett. 16 (2) (2017)
Tomer Y. Morad, Gil Shomron, Mattan Erez, Avinoam Kolodny, Uri C. Weiser
Optimizing Read-Once Data Flow in Big-Data Applications. IEEE Comput. Archit. Lett. 16 (1) (2017)
Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser
A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. IEEE Micro 37 (4) (2017)
Leonid Yavits, Amir Morad, Uri C. Weiser, Ran Ginosar
MultiAmdahl: Optimal Resource Allocation in Heterogeneous Architectures. CoRR (2017)
Efraim Rotem, Uri C. Weiser, Avi Mendelson, Ran Ginosar, Eliezer Weissmann, Yoni Aizik
H-EARtH: Heterogeneous Multicore Platform Energy Management. Computer 49 (10) (2016)
Leonid Yavits, Amir Morad, Ran Ginosar, Uri C. Weiser
Convex Optimization of Real Time SoC. CoRR (2016)
Tomer Y. Morad, Noam Shalev, Idit Keidar, Avinoam Kolodny, Uri C. Weiser
EFS: Energy-Friendly Scheduler for memory bandwidth constrained systems. J. Parallel Distributed Comput. 95 (2016)
Uri C. Weiser
Potential future research in computing: Heterogeneous systems, memory subsystems - Process-in-storage, or not to process-in-storage? That is the question. SAMOS (2016)
Leeor Peled, Shie Mannor, Uri C. Weiser, Yoav Etsion
Semantic locality and context-based prefetching using reinforcement learning. ISCA (2015)
Leonid Azriel, Avi Mendelson, Uri C. Weiser
Peripheral Memory: A Technique for Fighting Memory Bandwidth Bottleneck. IEEE Comput. Archit. Lett. 14 (1) (2015)
Efraim Rotem, Ran Ginosar, Avi Mendelson, Uri C. Weiser
Power and thermal constraints of modern system-on-a-chip computer. Microelectron. J. 46 (12) (2015)
Shahar Kvatinsky, Dmitry Belousov, Slavik Liman, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
MAGIC - Memristor-Aided Logic. IEEE Trans. Circuits Syst. II Express Briefs (11) (2014)
Amir Morad, Tomer Y. Morad, Leonid Yavits, Ran Ginosar, Uri C. Weiser
Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC. IEEE Comput. Archit. Lett. 13 (1) (2014)
Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies. IEEE Trans. Very Large Scale Integr. Syst. 22 (10) (2014)
Adi Fuchs, Shie Mannor, Uri C. Weiser, Yoav Etsion
Loop-Aware Memory Prefetching Using Code Block Working Sets. MICRO (2014)
Shahar Kvatinsky, Yuval H. Nacson, Yoav Etsion, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
Memristor-Based Multithreading. IEEE Comput. Archit. Lett. 13 (1) (2014)
Efraim Rotem, Uri C. Weiser, Avi Mendelson, Ahmad Yasin, Ran Ginosar
Energy management of highly dynamic server workloads in an heterogeneous data center. PATMOS (2014)
Efraim Rotem, Ran Ginosar, Uri C. Weiser, Avi Mendelson
Energy Aware Race to Halt: A Down to EARtH Approach for Platform Energy Management. IEEE Comput. Archit. Lett. 13 (1) (2014)
Tsahee Zidenberg, Isaac Keslassy, Uri C. Weiser
Optimal Resource Allocation with MultiAmdahl. Computer 46 (7) (2013)
Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
TEAM: ThrEshold Adaptive Memristor Model. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2013)
Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser
Task Scheduling Based On Thread Essence and Resource Limitations. J. Comput. 7 (1) (2012)
Tsahee Zidenberg, Isaac Keslassy, Uri C. Weiser
MultiAmdahl: How Should I Divide My Heterogenous Chip? IEEE Comput. Archit. Lett. 11 (2) (2012)
Tsahee Zidenberg, Isaac Keslassy, Uri C. Weiser
Multi-Amdahl: Optimal Resource Sharing with Multiple Program Execution Segments CoRR (2011)
Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman
Memristor-based IMPLY logic design procedure. ICCD (2011)
Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser
Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors. PAAP (2010)
Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser
Threads vs. caches: Modeling the behavior of parallel workloads. ICCD (2010)
Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser
Multiple clock and voltage domains for chip multi processors. MICRO (2009)
Zvika Guz, Evgeny Bolotin, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser
Many-Core vs. Many-Thread Machines: Stay Away From the Valley. IEEE Comput. Archit. Lett. 8 (1) (2009)
Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser
Utilizing shared data in chip multiprocessors with the nahalal architecture. SPAA (2008)
A. Elyada, Ran Ginosar, Uri C. Weiser
Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors. IEEE Trans. Very Large Scale Integr. Syst. 16 (9) (2008)
Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser
Nahalal: Cache Organization for Chip Multiprocessors. IEEE Comput. Archit. Lett. 6 (1) (2007)
Tomer Y. Morad, Uri C. Weiser, A. Kolodnyt, Mateo Valero, Eduard Ayguadé
Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors. IEEE Comput. Archit. Lett. 5 (1) (2006)
Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir
Interconnect-power dissipation in a microprocessor. SLIP (2004)
Michael Bekerman, Stéphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri C. Weiser
Correlated Load-Address Predictors. ISCA (1999)
Oded Lempel, Alex Peleg, Uri C. Weiser
Intel's MMX™ technology-a new instruction set extension. COMPCON (1997)
Alex Peleg, Sam Wilkie, Uri C. Weiser
Intel MMX for Multimedia PCs. Commun. ACM 40 (1) (1997)
Alex Peleg, Uri C. Weiser
MMX technology extension to the Intel architecture. IEEE Micro 16 (4) (1996)
Fabian Klass, Uri C. Weiser
Efficient Systolic Array for Matrix Multiplication. ICPP (3) (1991)