Avinoam Kolodny

Publication Activity (10 Years)

Years Active: 2003-2019
Publications (10 Years): 5

Top Venues

Integr.

IEEE J. Sel. Areas Commun.

ANCS

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Eitan Zahavi, Alexander Shpiner, Ori Rottenstreich, Avinoam Kolodny, Isaac Keslassy
Links as a Service (LaaS): Guaranteed Tenant Isolation in the Shared Cloud. IEEE J. Sel. Areas Commun. 37 (5) (2019)
Tomer Y. Morad, Gil Shomron, Mattan Erez, Avinoam Kolodny, Uri C. Weiser
Optimizing Read-Once Data Flow in Big-Data Applications. IEEE Comput. Archit. Lett. 16 (1) (2017)
Tomer Y. Morad, Noam Shalev, Idit Keidar, Avinoam Kolodny, Uri C. Weiser
EFS: Energy-Friendly Scheduler for memory bandwidth constrained systems. J. Parallel Distributed Comput. 95 (2016)
Ran Manevich, Israel Cidon, Avinoam Kolodny
Design and dynamic management of hierarchical NoCs. Microprocess. Microsystems 40 (2016)
Eitan Zahavi, Alexander Shpiner, Ori Rottenstreich, Avinoam Kolodny, Isaac Keslassy
Links as a Service (LaaS): Guaranteed Tenant Isolation in the Shared Cloud. ANCS (2016)
Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny
Average latency and link utilization analysis of heterogeneous wormhole NoCs. Integr. 51 (2015)
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing. Integr. 48 (2015)
Shahar Kvatinsky, Misbah Ramadan, Eby G. Friedman, Avinoam Kolodny
VTEAM: A General Model for Voltage-Controlled Memristors. IEEE Trans. Circuits Syst. II Express Briefs (8) (2015)
Eitan Zahavi, Alexander Shpiner, Ori Rottenstreich, Avinoam Kolodny, Isaac Keslassy
Links as a Service (LaaS): Feeling Alone in the Shared Cloud. CoRR (2015)
Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny, Michael Shabun, Nir Shmuel
Heterogeneous NoC Router Architecture. IEEE Trans. Parallel Distributed Syst. 26 (9) (2015)
Daniel Soudry, Dotan Di Castro, Asaf Gal, Avinoam Kolodny, Shahar Kvatinsky
Memristor-Based Multilayer Neural Networks With Online Gradient Descent Training. IEEE Trans. Neural Networks Learn. Syst. 26 (10) (2015)
Ravi Patel, Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny
Multistate Register Based on Resistive RAM. IEEE Trans. Very Large Scale Integr. Syst. 23 (9) (2015)
Shahar Kvatinsky, Dmitry Belousov, Slavik Liman, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
MAGIC - Memristor-Aided Logic. IEEE Trans. Circuits Syst. II Express Briefs (11) (2014)
Eitan Zahavi, Isaac Keslassy, Avinoam Kolodny
Distributed Adaptive Routing Convergence to Non-Blocking DCN Routing Assignments. IEEE J. Sel. Areas Commun. 32 (1) (2014)
Yifat Levy, Jehoshua Bruck, Yuval Cassuto, Eby G. Friedman, Avinoam Kolodny, Eitan Yaakobi, Shahar Kvatinsky
Logic operations in memory using a memristive Akers array. Microelectron. J. 45 (11) (2014)
Eitan Zahavi, Isaac Keslassy, Avinoam Kolodny
Quasi Fat Trees for HPC Clouds and Their Fault-Resilient Closed-Form Routing. Hot Interconnects (2014)
Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies. IEEE Trans. Very Large Scale Integr. Syst. 22 (10) (2014)
Ran Manevich, Leon Polishuk, Israel Cidon, Avinoam Kolodny
Designing single-cycle long links in hierarchical NoCs. Microprocess. Microsystems 38 (8) (2014)
Shahar Kvatinsky, Yuval H. Nacson, Yoav Etsion, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
Memristor-Based Multithreading. IEEE Comput. Archit. Lett. 13 (1) (2014)
Eitan Zahavi, Israel Cidon, Avinoam Kolodny
Gana: A novel low-cost conflict-free NoC architecture. ACM Trans. Embed. Comput. Syst. 12 (4) (2013)
Ran Manevich, Israel Cidon, Avinoam Kolodny
Dynamic traffic distribution among hierarchy levels in hierarchical Networks-on-Chip (NoCs). NOCS (2013)
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks. Integr. 46 (4) (2013)
Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
TEAM: ThrEshold Adaptive Memristor Model. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2013)
Ran Manevich, Leon Polishuk, Israel Cidon, Avinoam Kolodny
Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip. DSD (2013)
Shani Rehana, Or Turgeman, Ran Manevich, Avinoam Kolodny
ViLoCoN - An ultra-lightweight lossless VLSI video codec. SoCC (2013)
Ran Manevich, Israel Cidon, Avinoam Kolodny
Handling global traffic in future CMP NoCs. SLIP (2012)
Eitan Zahavi, Isaac Keslassy, Avinoam Kolodny
Distributed adaptive routing for big-data applications running on data center networks. ANCS (2012)
Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser
Task Scheduling Based On Thread Essence and Resource Limitations. J. Comput. 7 (1) (2012)
Inna Vaisband, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
Energy metrics for power efficient crosslink and mesh topologies. ISCAS (2012)
Victoria Vishnyakov, Eby G. Friedman, Avinoam Kolodny
Multi-aggressor capacitive and inductive coupling noise modeling and mitigation. Microelectron. J. 43 (4) (2012)
Roman Malits, Evgeny Bolotin, Avinoam Kolodny, Avi Mendelson
Exploring the limits of GPGPU scheduling in control flow bound applications. ACM Trans. Archit. Code Optim. 8 (4) (2012)
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
The complexity of VLSI power-delay optimization by interconnect resizing. J. Comb. Optim. 23 (2) (2012)
Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny
HNOCS: Modular open-source simulator for Heterogeneous NoCs. ICSAMOS (2012)
Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny
Optimizing heterogeneous NoC design. SLIP (2012)
Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, Shmuel Wimer
A Cost Effective Centralized Adaptive Routing for Networks-on-Chip. DSD (2011)
Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny
NoCs simulation framework for OMNeT++. NOCS (2011)
Evgeni Krimer, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter, Mattan Erez
Static timing analysis for modeling QoS in networks-on-chip. J. Parallel Distributed Comput. 71 (5) (2011)
Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman
Memristor-based IMPLY logic design procedure. ICCD (2011)
Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny
Delay analysis of wormhole based heterogeneous NoC. NOCS (2011)
Yoni Aizik, Avinoam Kolodny
Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints. VLSI Design 2011 (2011)
Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny
An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm. ISCAS (2011)
Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser
Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors. PAAP (2010)
Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. IEEE Trans. Very Large Scale Integr. Syst. 18 (8) (2010)
Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. IEEE Trans. Very Large Scale Integr. Syst. 18 (5) (2010)
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
Timing-driven variation-aware nonuniform clock mesh synthesis. ACM Great Lakes Symposium on VLSI (2010)
Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny
Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study. DATE (2010)
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
Interconnect power and delay optimization by dynamic programming in gridded design rules. ISPD (2010)
Gregory Sizikov, Avinoam Kolodny, Eby G. Friedman, Michael Zelikson
Efficiency optimization of integrated DC-DC buck converters. ICECS (2010)
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
Interconnect Bundle Sizing Under Discrete Design Rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (10) (2010)
Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny
Performance and Power Aware CMP Thread Allocation Modeling. HiPEAC (2010)
Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter
Centralized Adaptive Routing for NoCs. IEEE Comput. Archit. Lett. 9 (2) (2010)
Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam Kolodny, Ran Ginosar
Asynchronous Current Mode Serial Communication. IEEE Trans. Very Large Scale Integr. Syst. 18 (7) (2010)
Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny
The Devolution of Synchronizers. ASYNC (2010)
Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser
Threads vs. caches: Modeling the behavior of parallel workloads. ICCD (2010)
Isask'har Walter, Israel Cidon, Avinoam Kolodny, Daniel Sigalov
The era of many-modules SoC: revisiting the NoC mapping problem. NoCArc@MICRO (2009)
Ran Manevich, Isask'har Walter, Israel Cidon, Avinoam Kolodny
Best of both worlds: A bus enhanced NoC (BENoC). NOCS (2009)
Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny
QNoC asynchronous router. Integr. 42 (2) (2009)
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
Power-delay optimization in VLSI microprocessors by wire spacing. ACM Trans. Design Autom. Electr. Syst. 14 (4) (2009)
Avinoam Kolodny, Li-Shiuan Peh
Special Section on International Symposium on Networks-on-Chip (NOCS). IEEE Trans. Very Large Scale Integr. Syst. 17 (3) (2009)
Evgeni Krimer, Mattan Erez, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter
Packet-level static timing analysis for NoCs. NOCS (2009)
Zvika Guz, Evgeny Bolotin, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser
Many-Core vs. Many-Thread Machines: Stay Away From the Valley. IEEE Comput. Archit. Lett. 8 (1) (2009)
Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny
The design of a latency constrained, power optimized NoC for a 4G SoC. NOCS (2009)
Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
Power efficient tree-based crosslinks for skew reduction. ACM Great Lakes Symposium on VLSI (2009)
Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar
Parallel vs. serial on-chip communication. SLIP (2008)
Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny
On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 16 (7) (2008)
Isask'har Walter, Israel Cidon, Avinoam Kolodny
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP. IEEE Comput. Archit. Lett. 7 (2) (2008)
Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser
Utilizing shared data in chip multiprocessors with the nahalal architecture. SPAA (2008)
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
On optimal ordering of signals in parallel wire bundles. Integr. 41 (2) (2008)
Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
Timing optimization in logic with interconnect. SLIP (2008)
Mikhail Popovich, Michael Sotman, Avinoam Kolodny, Eby G. Friedman
Effective Radii of On-Chip Decoupling Capacitors. IEEE Trans. Very Large Scale Integr. Syst. 16 (7) (2008)
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
Timing-aware power-optimal ordering of signals. ACM Trans. Design Autom. Electr. Syst. 13 (4) (2008)
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny
The Power of Priority: NoC Based Distributed Cache Coherency. NOCS (2007)
Avinoam Kolodny
Networks on chips: keeping up with Rent's rule and Moore's law. SLIP (2007)
Michael Behar, Avi Mendelson, Avinoam Kolodny
Trace cache sampling filter. ACM Trans. Comput. Syst. 25 (1) (2007)
Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny
Access Regulation to Hot-Modules in Wormhole NoCs. NOCS (2007)
Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
Network Delays and Link Capacities in Application-Specific Wormhole NoCs. VLSI Design 2007 (2007)
Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser
Nahalal: Cache Organization for Chip Multiprocessors. IEEE Comput. Archit. Lett. 6 (1) (2007)
Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. ASYNC (2007)
Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
Routing table minimization for irregular mesh NoCs. DATE (2007)
Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
Efficient link capacity and QoS design for network-on-chip. DATE (2006)
Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu
Maximum effective distance of on-chip decoupling capacitors in power distribution grids. ACM Great Lakes Symposium on VLSI (2006)
Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny
Fast Asynchronous Shift Register for Bit-Serial Communication. ASYNC (2006)
Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny
Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization. IEEE Trans. Very Large Scale Integr. Syst. 14 (11) (2006)
Shmuel Wimer, Shay Michaely, Konstantin Moiseev, Avinoam Kolodny
Optimal bus sizing in migration of processor design. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2006)
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. ISCAS (2006)
Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman
On-die decoupling capacitance: frequency domain analysis of activity radius. ISCAS (2006)
Noam Dolev, Avner Kornfeld, Avinoam Kolodny
Comparison of Sigma-delta Converter Circuit Architectures in Digital Cmos Technology. J. Circuits Syst. Comput. 14 (3) (2005)
Michael Behar, Avi Mendelson, Avinoam Kolodny
Trace Cache Sampling Filter. IEEE PACT (2005)
Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny
On-chip power distribution grids with multiple supply voltages for high performance integrated circuits. ACM Great Lakes Symposium on VLSI (2005)
Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny
Low-leakage repeaters for NoC interconnects. ISCAS (1) (2005)
Shay Michaely, Shmuel Wimer, Avinoam Kolodny
Optimal resizing of bus wires in layout migration. ICECS (2004)
Arkadiy Morgenshtein, Evgeny Bolotin, Israel Cidon, Avinoam Kolodny, Ran Ginosar
Micro-modem - reliability solution for NoC communications. ICECS (2004)
Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir
Interconnect-power dissipation in a microprocessor. SLIP (2004)
Anastasia Barger, David Goren, Avinoam Kolodny
Design and modelling of network on chip interconnects using transmission lines. ICECS (2004)
Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar
Comparative analysis of serial vs parallel links in NoC. SoC (2004)
Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
QNoC: QoS architecture and design process for network on chip. J. Syst. Archit. 50 (2-3) (2004)
Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny
Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization. ICECS (2004)
Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
Cost considerations in network on chip. Integr. 38 (1) (2004)
Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny
Automatic hardware-efficient SoC integration by QoS network on chip. ICECS (2004)
Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny
Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects. VLSI-SOC (2003)

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Publication Activity (10 Years)

Top Topics

Top Venues

Avinoam Kolodny