Shmuel Wimer

Publication Activity (10 Years)

Years Active: 1983-2023
Publications (10 Years): 16

Top Topics

Energy Efficient

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Oper. Res. Lett.

Comput. Electr. Eng.

Publications

Binyamin Frankel, Shmuel Wimer
A Self-Refreshable Bit-Cell for Single-Cycle Refreshing of Embedded Memories. IEEE Trans. Computers 72 (2) (2023)
Binyamin Frankel, Eyal Sarfati, Davide Rossi, Shmuel Wimer
Energy Efficiency of Opportunistic Refreshing for Gain-Cell Embedded DRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (4) (2023)
Nir Halman, Shmuel Wimer
Resource allocation in rooted trees subject to sum constraints and nonlinear cost functions. Inf. Process. Lett. 170 (2021)
Eyal Sarfati, Binyamin Frankel, Yitzhak Birk, Shmuel Wimer
Accurate Shielded Interconnect Delay Estimation by Reconfigurable Ring Oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Roi Herman, Binyamin Frankel, Shmuel Wimer
Optimal queuing-based memory refreshing algorithm for energy efficient processors. Comput. Electr. Eng. 71 (2018)
Binyamin Frankel, Roi Herman, Shmuel Wimer
Queuing-Based eDRAM Refreshing for Ultra-Low Power Processors. IEEE Trans. Computers 67 (9) (2018)
Eyal Sarfati, Binyamin Frankel, Yitzhak Birk, Shmuel Wimer
Optimal VLSI Delay Tuning by Space Tapering With Clock-Tree Application. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2017)
Doron Gluzer, Shmuel Wimer
Probability-Driven Multibit Flip-Flop Integration With Clock Gating. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Amir Albeck, Shmuel Wimer
Energy efficient computing by multi-mode addition. Integr. 55 (2016)
Amit Kazimirsky, Shmuel Wimer
Opportunistic Refreshing Algorithm for eDRAM Memories. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2016)
Binyamin Frankel, Shmuel Wimer
Optimal VLSI Delay Tuning by Wire Shielding. J. Optim. Theory Appl. 170 (3) (2016)
Shmuel Wimer, Israel Koren
Energy efficient deeply fused dot-product multiplication architecture. ASAP (2016)
Shmuel Wimer
Optimal weight allocation in rooted trees. J. Comb. Optim. 31 (3) (2016)
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing. Integr. 48 (2015)
Shmuel Wimer, Amnon Stanislavsky
Energy efficient hybrid adder architecture. Integr. 48 (2015)
Yakov Kaplan, Shmuel Wimer
Mixing Drivers in Clock-Tree for Power Supply Noise Reduction. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2015)
Shmuel Wimer, Doron Gluzer, Uri Wimer
Using well-solvable minimum cost exact covering for VLSI clock energy minimization. Oper. Res. Lett. 42 (5) (2014)
Shmuel Wimer
Easy and difficult exact covering problems arising in VLSI power reduction by clock gating. Discret. Optim. 14 (2014)
Eugene Shaphir, Ron Y. Pinter, Shmuel Wimer
Cell-based interconnect migration by hierarchical optimization. Integr. 47 (2) (2014)
Shmuel Wimer, Amir Albeck, Israel Koren
A low energy dual-mode adder. Comput. Electr. Eng. 40 (5) (2014)
Shmuel Wimer, Israel Koren
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating. IEEE Trans. Very Large Scale Integr. Syst. 22 (4) (2014)
Shmuel Wimer
Planar CMOS to multi-gate layout conversion for maximal fin utilization. Integr. 47 (1) (2014)
Shmuel Wimer, Arye Albahari
A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2014)
Itamar Levi, Amir Albeck, Alexander Fish, Shmuel Wimer
A Low Energy and High Performance ${\rm DM}^{2}$ Adder. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2014)
Shmuel Wimer
On optimal flip-flop grouping for VLSI power minimization. Oper. Res. Lett. 41 (5) (2013)
Ben Emanuel, Shmuel Wimer, Gershon Wolansky
Using well-solvable quadratic assignment problems for VLSI interconnect applications. Discret. Appl. Math. 160 (4-5) (2012)
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
The complexity of VLSI power-delay optimization by interconnect resizing. J. Comb. Optim. 23 (2) (2012)
Shmuel Wimer, Israel Koren
The Optimal Fan-Out of Clock Network for Power Minimization by Adaptive Gating. IEEE Trans. Very Large Scale Integr. Syst. 20 (10) (2012)
Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, Shmuel Wimer
A Cost Effective Centralized Adaptive Routing for Networks-on-Chip. DSD (2011)
Eranda Çela, Nina S. Schmuck, Shmuel Wimer, Gerhard J. Woeginger
The Wiener maximum quadratic assignment problem. Discret. Optim. 8 (3) (2011)
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
Interconnect power and delay optimization by dynamic programming in gridded design rules. ISPD (2010)
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
Interconnect Bundle Sizing Under Discrete Design Rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (10) (2010)
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
Power-delay optimization in VLSI microprocessors by wire spacing. ACM Trans. Design Autom. Electr. Syst. 14 (4) (2009)
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
On optimal ordering of signals in parallel wire bundles. Integr. 41 (2) (2008)
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
Timing-aware power-optimal ordering of signals. ACM Trans. Design Autom. Electr. Syst. 13 (4) (2008)
Shmuel Wimer, Shay Michaely, Konstantin Moiseev, Avinoam Kolodny
Optimal bus sizing in migration of processor design. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2006)
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. ISCAS (2006)
Shay Michaely, Shmuel Wimer, Avinoam Kolodny
Optimal resizing of bus wires in layout migration. ICECS (2004)
Shmuel Wimer, Israel Koren, Israel Cederbaum
On Paths with the Shortest Average Arc Length in Weighted Graphs. Discret. Appl. Math. 45 (2) (1993)
Jack A. Feldman, Israel A. Wagner, Shmuel Wimer
An efficient algorithm for some multirow layout problems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (8) (1993)
Israel Cederbaum, Israel Koren, Shmuel Wimer
Balanced Block Spacing for VLSI Layout. Discret. Appl. Math. 40 (3) (1992)
Reuven Bar-Yehuda, Jack A. Feldman, Ron Y. Pinter, Shmuel Wimer
Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (7) (1989)
Shmuel Wimer, Israel Koren, Israel Cederbaum
Optimal aspect ratios of building blocks in VLSI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (2) (1989)
Shmuel Wimer, Israel Koren
Analysis of strategies for constructive general block placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (3) (1988)
Shmuel Wimer, Israel Koren, Israel Cederbaum
Optimal Aspect Ratios of Building Blocks in VLSI. DAC (1988)
Shmuel Wimer, Ron Y. Pinter, Jack A. Feldman
Optimal Chaining of CMOS Transistors in a Functional Cell. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 (5) (1987)
Shmuel Wimer, N. Sharfman
HOPLA-PLA optimization and synthesis. DAC (1983)