The complexity of VLSI power-delay optimization by interconnect resizing.
Konstantin MoiseevAvinoam KolodnyShmuel WimerPublished in: J. Comb. Optim. (2012)
Keyphrases
- power dissipation
- power consumption
- low power
- high speed
- chip design
- digital signal processing
- optimization algorithm
- global optimization
- worst case
- power management
- optimization problems
- signal processing
- optimization process
- power losses
- optimization model
- constrained optimization
- computational complexity
- design methodology
- finite state machines
- image processing
- low cost
- cmos technology
- image resizing
- evolutionary algorithm
- power transmission