Arkadiy Morgenshtein

Publication Activity (10 Years)

Years Active: 2002-2017
Publications (10 Years): 3

Top Topics

Comparative Study

Learning Automata

Energy Dissipation

Top Venues

Publications

Wisam Kadry, Dmitry Krestyashyn, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin, Jin Sung Park, Sung-Boem Park, Wookyeong Jeong, Jae-Cheol Son
Test Generation Methods for Utilization Improvement of Hardware-Accelerated Simulation Platforms. IEEE Des. Test 34 (1) (2017)
Doowon Lee, Tom Kolan, Arkadiy Morgenshtein, Vitali Sokhin, Ronny Morad, Avi Ziv, Valeria Bertacco
Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification. DAC (2016)
Wisam Kadry, Dmitry Krestyashyn, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin, Jin Sung Park, Sung-Boem Park, Wookyeong Jeong, Jae-Cheol Son
Comparative study of test generation methods for simulation accelerators. DATE (2015)
Ophir Friedler, Wisam Kadry, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin
Effective post-silicon failure localization using dynamic program slicing. DATE (2014)
Arkadiy Morgenshtein, Viacheslav Yuzhaninov, Alexey Kovshilovsky, Alexander Fish
Full-Swing Gate Diffusion Input logic - Case-study of low-power CLA adder design. Integr. 47 (1) (2014)
Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. IEEE Trans. Very Large Scale Integr. Syst. 18 (8) (2010)
Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. IEEE Trans. Very Large Scale Integr. Syst. 18 (5) (2010)
Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar
Parallel vs. serial on-chip communication. SLIP (2008)
Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
Timing optimization in logic with interconnect. SLIP (2008)
Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny
Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization. IEEE Trans. Very Large Scale Integr. Syst. 14 (11) (2006)
Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny
Low-leakage repeaters for NoC interconnects. ISCAS (1) (2005)
Arkadiy Morgenshtein, Evgeny Bolotin, Israel Cidon, Avinoam Kolodny, Ran Ginosar
Micro-modem - reliability solution for NoC communications. ICECS (2004)
Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar
Asynchronous gate-diffusion-input (GDI) circuits. IEEE Trans. Very Large Scale Integr. Syst. 12 (8) (2004)
Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar
Comparative analysis of serial vs parallel links in NoC. SoC (2004)
Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny
Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization. ICECS (2004)
Liby Sudakov-Boreysha, Arkadiy Morgenshtein, Uri Dinnar, Yael Nemirovsky
ISFET CMOS compatible design and encapsulation challenges. ICECS (2004)
Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner
An efficient implementation of D-Flip-Flop using the GDI technique. ISCAS (2) (2004)
Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny
Automatic hardware-efficient SoC integration by QoS network on chip. ICECS (2004)
Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny
Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects. VLSI-SOC (2003)
Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner
Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization. ISCAS (1) (2002)
Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner
Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits. IEEE Trans. Very Large Scale Integr. Syst. 10 (5) (2002)