Ronny Ronen

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 44

Top Topics

Convolutional Neural Network

Computing Power

Fast Fourier Transform

Top Venues

ACM J. Emerg. Technol. Comput. Syst.

Publications

Ben Perach, Ronny Ronen, Benny Kimelfeld, Shahar Kvatinsky
Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics. IEEE Trans. Emerg. Top. Comput. 12 (1) (2024)
Ben Perach, Ronny Ronen, Shahar Kvatinsky
Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory. CoRR (2023)
Ben Perach, Ronny Ronen, Shahar Kvatinsky
Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory. CoRR (2023)
Orian Leitersdorf, Yahav Boneh, Gonen Gazit, Ronny Ronen, Shahar Kvatinsky
FourierPIM: High-Throughput In-Memory Fast Fourier Transform and Polynomial Multiplication. CoRR (2023)
Ben Perach, Ronny Ronen, Shahar Kvatinsky
Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory. NEWCAS (2023)
Ben Perach, Ronny Ronen, Shahar Kvatinsky
Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory. SOCC (2023)
Ben Perach, Ronny Ronen, Shahar Kvatinsky
On Consistency for Bulk-Bitwise Processing-in-Memory. HPCA (2023)
Orian Leitersdorf, Dean Leitersdorf, Jonathan Gal, Mor M. Dahan, Ronny Ronen, Shahar Kvatinsky
AritPIM: High-Throughput In-Memory Arithmetic. IEEE Trans. Emerg. Top. Comput. 11 (3) (2023)
Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
CUDA-PIM: End-to-End Integration of Digital Processing-in-Memory from High-Level C++ to Microarchitectural Design. CoRR (2023)
Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
ConvPIM: Evaluating Digital Processing-in-Memory through Convolutional Neural Network Acceleration. CoRR (2023)
Ronny Ronen, Adi Eliahu, Orian Leitersdorf, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky
The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems. ACM J. Emerg. Technol. Comput. Syst. 18 (2) (2022)
Batel Oved, Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory. CoRR (2022)
Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
PartitionPIM: Practical Memristive Partitions for Fast Processing-in-Memory. CoRR (2022)
Ben Perach, Ronny Ronen, Benny Kimelfeld, Shahar Kvatinsky
PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics. CoRR (2022)
Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic. CoRR (2022)
Ben Perach, Ronny Ronen, Shahar Kvatinsky
On Consistency for Bulk-Bitwise Processing-in-Memory. CoRR (2022)
Wei Wang, Barak Hoffer, Tzofnat Greenberg-Toledo, Yang Li, Minhui Zou, Eric Herbelin, Ronny Ronen, Xiaoxin Xu, Yulin Zhao, Jianguo Yang, Shahar Kvatinsky
Efficient Training of the Memristive Deep Belief Net Immune to Non-Idealities of the Synaptic Devices. CoRR (2022)
Marcel Khalifa, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, Shahar Kvatinsky
FiltPIM: In-Memory Filter for DNA Sequencing. CoRR (2022)
Orian Leitersdorf, Dean Leitersdorf, Jonathan Gal, Mor M. Dahan, Ronny Ronen, Shahar Kvatinsky
AritPIM: High-Throughput In-Memory Arithmetic. CoRR (2022)
Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky
abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory. CoRR (2022)
Batel Oved, Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory. MOCAST (2022)
Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic. ISCAS (2022)
Wei Wang, Barak Hoffer, Tzofnat Greenberg-Toledo, Yang Li, Minhui Zou, Eric Herbelin, Ronny Ronen, Xiaoxin Xu, Yulin Zhao, Jianguo Yang, Shahar Kvatinsky
Efficient Training of the Memristive Deep Belief Net Immune to Non-Idealities of the Synaptic Devices. Adv. Intell. Syst. 4 (5) (2022)
Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
MultPIM: Fast Stateful Multiplication for Processing-in-Memory. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
Making Memristive Processing-in-Memory Reliable. ICECS (2021)
Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
Making Memristive Processing-in-Memory Reliable. CoRR (2021)
Adi Eliahu, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky
multiPULPly: A Multiplication Engine for Accelerating Neural Networks on Ultra-low-power Architectures. ACM J. Emerg. Technol. Comput. Syst. 17 (2) (2021)
Orian Leitersdorf, Ben Perach, Ronny Ronen, Shahar Kvatinsky
Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory. CoRR (2021)
Orian Leitersdorf, Ben Perach, Ronny Ronen, Shahar Kvatinsky
Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory. DAC (2021)
Marcel Khalifa, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, Shahar Kvatinsky
FiltPIM: In-Memory Filter for DNA Sequencing. ICECS (2021)
Ronny Ronen, Adi Eliahu, Orian Leitersdorf, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky
The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems. CoRR (2021)
Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
MultPIM: Fast Stateful Multiplication for Processing-in-Memory. CoRR (2021)
Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky
CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. ICCAD (2020)
Rotem Ben Hur, Ronny Ronen, Ameer Haj Ali, Debjyoti Bhattacharjee, Adi Eliahu, Natan Peled, Shahar Kvatinsky
SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky
CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. CoRR (2020)
Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky
abstractPIM: Bridging the Gap Between Processing-In-Memory Technology and Instruction Set Architecture. VLSI-SOC (2020)
Natan Peled, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky
X-MAGIC: Enhancing PIM Using Input Overwriting Capabilities. VLSI-SOC (2020)
Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky
abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory. VLSI-SoC (Selected Papers) (2020)
Kunal Korgaonkar, Ronny Ronen, Anupam Chattopadhyay, Shahar Kvatinsky
The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm. CoRR (2019)
Nishil Talati, Heonjae Ha, Ben Perach, Ronny Ronen, Shahar Kvatinsky
CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM. IEEE Micro 39 (1) (2019)
Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Shahar Kvatinsky
IMAGING: In-Memory AlGorithms for Image processiNG. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2018)
Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Shahar Kvatinsky
Not in Name Alone: A Memristive Memory Processing Unit for Real In-Memory Processing. IEEE Micro 38 (5) (2018)
Nishil Talati, Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky
Practical challenges in delivering the promises of real processing-in-memory machines. DATE (2018)
Ronny Ronen
Why & When Deep Learning Works: Looking Inside Deep Learnings. CoRR (2017)
Kenneth Czechowski, Victor W. Lee, Ed Grochowski, Ronny Ronen, Ronak Singhal, Richard W. Vuduc, Pradeep Dubey
Improving the energy efficiency of Big Cores. ISCA (2014)
Ronny Ronen
Larrabee: a many-core Intel architecture for visual computing. Conf. Computing Frontiers (2009)
Shoumeng Yan, Xiaocheng Zhou, Ying Gao, Hu Chen, Sai Luo, Peinan Zhang, Naveen Cherukuri, Ronny Ronen, Bratin Saha
Terascale chip multiprocessor memory hierarchy and programming model. HiPC (2009)
Amit Golander, Shlomo Weiss, Ronny Ronen
Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture. IEEE Trans. Circuits Syst. II Express Briefs (6) (2009)
Bratin Saha, Xiaocheng Zhou, Hu Chen, Ying Gao, Shoumeng Yan, Mohan Rajagopalan, Jesse Fang, Peinan Zhang, Ronny Ronen, Avi Mendelson
Programming model for a heterogeneous x86 platform. PLDI (2009)
Amit Golander, Shlomo Weiss, Ronny Ronen
DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals. IEEE Comput. Archit. Lett. 7 (2) (2008)
Ronny Ronen, Antonio González
Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences. IEEE Micro 27 (1) (2007)
Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang
Best of Both Latency and Throughput. ICCD (2004)
Baruch Solomon, Avi Mendelson, Ronny Ronen, Doron Orenstein, Yoav Almog
Micro-operation cache: a power aware frontend for variable instruction length ISA. IEEE Trans. Very Large Scale Integr. Syst. 11 (5) (2003)
Roni Rosner, Micha Moffie, Yiannakis Sazeides, Ronny Ronen
Selecting long atomic traces for high coverage. ICS (2003)
Aviad Cohen, Lev Finkelstein, Avi Mendelson, Ronny Ronen, Dmitry Rudoy
On Estimating Optimal Performance of CPU Dynamic Thermal Management. IEEE Comput. Archit. Lett. 2 (2003)
Ronny Ronen, Avi Mendelson, Konrad Lai, Shih-Lien Lu, Fred J. Pollack, John Paul Shen
Coming challenges in microarchitecture and architecture. Proc. IEEE 89 (3) (2001)
Baruch Solomon, Avi Mendelson, Doron Orenstein, Yoav Almog, Ronny Ronen
Micro-operation cache: a power aware frontend for the variable instruction length ISA. ISLPED (2001)
Roni Rosner, Avi Mendelson, Ronny Ronen
Filtering Techniques to Improve Trace-Cache Efficiency. IEEE PACT (2001)
Amir Roth, Ronny Ronen, Avi Mendelson
Dynamic techniques for load and load-use scheduling. Proc. IEEE 89 (11) (2001)
Stéphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen
eXtended Block Cache. HPCA (2000)
Michael Bekerman, Adi Yoaz, Freddy Gabbay, Stéphan Jourdan, Maxim Kalaev, Ronny Ronen
Early load address resolution via register tracking. ISCA (2000)
Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan Jourdan
Speculation Techniques for Improving Load Related Instruction Scheduling. ISCA (1999)
Michael Bekerman, Stéphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri C. Weiser
Correlated Load-Address Predictors. ISCA (1999)
Stéphan Jourdan, Ronny Ronen, Michael Bekerman, Bishara Shomar, Adi Yoaz
A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification. MICRO (1998)