Shlomo Weiss

Publication Activity (10 Years)

Years Active: 1983-2021
Publications (10 Years): 6

Top Topics

Genome Sequencing

Digital Signal Processors

Computational Methods

Top Venues

IEEE Embed. Syst. Lett.

IEEE Trans. Very Large Scale Integr. Syst.

J. Comput. Phys.

Publications

Junyi Zhou, Roger Kahn, Shlomo Weiss
A novel low power hybrid cache using GC-EDRAM cells. Integr. 81 (2021)
David Uzan, Roger Kahn, Shlomo Weiss
Perceptron based filtering of futile prefetches in embedded VLIW DSPs. J. Syst. Archit. 110 (2020)
Ben Perach, Shlomo Weiss
SiMT-DSP: A Massively Multithreaded DSP Architecture. IEEE Trans. Very Large Scale Integr. Syst. 26 (8) (2018)
Konstantin Berestizshevsky, Shlomo Weiss
Decoupled Branch Predictor for Embedded DSP. IEEE Embed. Syst. Lett. 10 (3) (2018)
Gadi Oxman, Shlomo Weiss
Deflection Routing in Hierarchical Mesh NoCs. IEEE Embed. Syst. Lett. 8 (2) (2016)
Gadi Oxman, Shlomo Weiss
An NoC Simulator That Supports Deflection Routing, GPU/CPU Integration, and Co-Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (10) (2016)
Gadi Oxman, Shlomo Weiss
DNOC: an accurate and fast virtual channel and deflection routing network-on-chip simulator. ISPASS (2015)
Gadi Oxman, Shlomo Weiss
RIDER: Ring deflection router with buffers. Des. Autom. Embed. Syst. 18 (3-4) (2014)
Sagi Manole, Amit Golander, Shlomo Weiss
Protein Sequence Pattern Matching: Leveraging Application Specific Hardware Accelerators. IEEE Trans. Computers 63 (2) (2014)
Doron Sabo, Oded Barzelay, Shlomo Weiss, Miriam Furst
Fast evaluation of a time-domain non-linear cochlear model on GPUs. J. Comput. Phys. 265 (2014)
Alexei Jolondz, Shlomo Weiss, Amit Golander
L1-L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters. IEEE Trans. Very Large Scale Integr. Syst. 22 (10) (2014)
Gadi Oxman, Shlomo Weiss, Yair Be'ery
Computational methods for Conway's Game of Life cellular automaton. J. Comput. Sci. 5 (1) (2014)
Doron Sabo, Shlomo Weiss, Miriam Furst
A Parallel Algorithm for a Physiological Non-Linear Model of the Cochlea. ICCS (2013)
Eran Shifer, Shlomo Weiss
Low-latency adaptive mode transitions and hierarchical power management in asymmetric clustered cores. ACM Trans. Archit. Code Optim. 10 (3) (2013)
Omer Zilberberg, Shlomo Weiss, Sivan Toledo
Phase-change memory: An architectural perspective. ACM Comput. Surv. 45 (3) (2013)
Simon Grinberg, Shlomo Weiss
Architectural virtualization extensions: A systems perspective. Comput. Sci. Rev. 6 (5-6) (2012)
Nadav Cohen, Shlomo Weiss
Complex Floating Point - A Novel Data Word Representation for DSP Processors. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2012)
Gadi Oxman, Shlomo Weiss, Yitzhak (Tsahi) Birk
Buffered deflection routing for networks-on-chip. INA-OCMC@HiPEAC (2012)
Gal Motika, Shlomo Weiss
Virtio network paravirtualization driver: Implementation and performance of a de-facto standard. Comput. Stand. Interfaces 34 (1) (2012)
Gadi Oxman, Shlomo Weiss, Yitzhak (Tsahi) Birk
Streamlined Network-on-Chip for Multicore Embedded Architectures. ARCS (2012)
Nadav Levison, Shlomo Weiss
Low power branch prediction for embedded application processors. ISLPED (2010)
Nadav Levison, Shlomo Weiss
Branch target buffer design for embedded processors. Microprocess. Microsystems 34 (6) (2010)
Roger Kahn, Shlomo Weiss
Reducing leakage power with BTB access prediction. Integr. 43 (1) (2010)
Amit Golander, Shlomo Weiss
Reexecution and Selective Reuse in Checkpoint Processors. Trans. High Perform. Embed. Archit. Compil. 2 (2009)
Ron Gabor, Avi Mendelson, Shlomo Weiss
Service level agreement for multithreaded processors. ACM Trans. Archit. Code Optim. 6 (2) (2009)
Amit Golander, Shlomo Weiss, Ronny Ronen
Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture. IEEE Trans. Circuits Syst. II Express Briefs (6) (2009)
Amit Golander, Shlomo Weiss
Checkpoint allocation and release. ACM Trans. Archit. Code Optim. 6 (3) (2009)
Amit Golander, Shlomo Weiss
Hiding the misprediction penalty of a resource-efficient high-performance processor. ACM Trans. Archit. Code Optim. 4 (4) (2008)
Amit Golander, Shlomo Weiss, Ronny Ronen
DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals. IEEE Comput. Archit. Lett. 7 (2) (2008)
Roger Kahn, Shlomo Weiss
Thrifty BTB: A comprehensive solution for dynamic power reduction in branch target buffers. Microprocess. Microsystems 32 (8) (2008)
Ron Gabor, Shlomo Weiss, Avi Mendelson
Fairness enforcement in switch on event multithreading. ACM Trans. Archit. Code Optim. 4 (3) (2007)
Ron Gabor, Shlomo Weiss, Avi Mendelson
Fairness and Throughput in Switch on Event Multithreading. MICRO (2006)
Yehuda Sadeh Weinraub, Shlomo Weiss
Power-aware out-of-order issue logic in high-performance microprocessors. Microprocess. Microsystems 30 (7) (2006)
Doron Nakar, Shlomo Weiss
Selective main memory compression by identifying program phase changes. WMPI (2004)
Tomer Karin, Shlomo Weiss
Programming Windows NT device drivers to operate non-interrupting embedded devices. Microprocess. Microsystems 28 (1) (2004)
Avishay Orpaz, Shlomo Weiss
Pattern Matching by means of Multi-Resolution Compression. DCC (2003)
Shlomo Weiss, Roman Tsikel
Approximate prefix coding for system-on-a-chip programs. J. Syst. Archit. 48 (13-15) (2003)
Tal Oved, Shlomo Weiss
Embedded instruction memory in automotive engine controllers. IEEE Trans. Veh. Technol. 52 (1) (2003)
Shlomo Weiss, Shay Beren
Class-Based Decompressor Design for Compressed Instruction Memory in Embedded Processors. IEEE Trans. Computers 52 (11) (2003)
Ehud Finkelstein, Shlomo Weiss
A PCI bus simulation framework and some simulation results on PCI standard 2.1 latency limitations. J. Syst. Archit. 47 (9) (2002)
Avishay Orpaz, Shlomo Weiss
A study of CodePack: optimizing embedded code space. CODES (2002)
Shlomo Weiss, Shay Beren
HW/SW partitioning of an embedded instruction memory decompressor. CODES (2001)
Shlomo Weiss, Ehud Finkelstein
Extending PCI Performance Beyond the Desktop. Computer 32 (6) (1999)
Ehud Finkelstein, Shlomo Weiss
Microprocessor system buses: A case study. J. Syst. Archit. 45 (12-13) (1999)
Shlomo Reches, Shlomo Weiss
Implementation and Analysis of Path History in Dynamic Branch Prediction Schemes. IEEE Trans. Computers 47 (8) (1998)
Eitan Federovsky, Meir Feder, Shlomo Weiss
Branch Prediction Based on Universal Data Compression Algorithms. ISCA (1998)
Shlomo Weiss, A. Goldstein
Floating point micropipeline performance. J. Syst. Archit. 45 (1) (1998)
Shlomo Reches, Shlomo Weiss
Implementation and Analysis of Path History in Dynamic Branch Prediction Schemes. International Conference on Supercomputing (1997)
Shlomo Weiss
Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors. HPCA (1995)
James E. Smith, Shlomo Weiss
PowerPC 601 and Alpha 21064: A Tale of Two RISCs. Computer 27 (6) (1994)
Shlomo Weiss
Optimizing a superscalar machine to run vector code. IEEE Parallel Distributed Technol. Syst. Appl. 1 (2) (1993)
Ravi Ganesan, Shlomo Weiss
Scalar Memory References in Pipelined Multiprocessors: A Performance Study. IEEE Trans. Software Eng. 18 (1) (1992)
Shlomo Weiss
Memory conflict resolution in vector supercomputers. J. Supercomput. 6 (1) (1992)
Shlomo Weiss
Multiple-Port Memory Access in Decoupled Architecture Processors. ICPP (1) (1991)
Shlomo Weiss, James E. Smith
A study of scalar compilation techniques for pipelined supercomputers. ACM Trans. Math. Softw. 16 (3) (1990)
Shlomo Weiss
Scalar supercomputer architecture. Proc. IEEE 77 (12) (1989)
Shlomo Weiss
An Aperiodic Storage Scheme to Reduce Memory Conflicts in Vector Processors. ISCA (1989)
Shlomo Weiss, James E. Smith
A Study of Scalar Compilation Techniques for Pipelined Supercomputers. ASPLOS (1987)
James E. Smith, Shlomo Weiss, Nicholas Y. Pang
A Simulation Study of Decoupled Architecture Computers. IEEE Trans. Computers 35 (8) (1986)
Shlomo Weiss, Katie Rotzell, Tom Rhyne, Arny Goldfein
DOSS: a storage system for design data. DAC (1986)
Shlomo Weiss, James E. Smith
Instruction Issue Logic in Pipelined Supercomputers. IEEE Trans. Computers 33 (11) (1984)
Randy H. Katz, Shlomo Weiss
Design transaction management. DAC (1984)
Shlomo Weiss, James E. Smith
Instruction Issue Logic for Pipelined Supercomputers. ISCA (1984)
Shlomo Weiss
Recovery of In-Memory Data Structures for Interactive Update Applications. COMPCON (1984)
Randy H. Katz, Shlomo Weiss
Chip assemblers: Concepts and capabilities. DAC (1983)