James E. Smith

Publication Activity (10 Years)

Years Active: 1978-2017
Publications (10 Years): 1

Top Topics

Spatial And Temporal

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Top Venues

Publications

James E. Smith
Research Agenda: Spacetime Computation and the Neocortex. IEEE Micro 37 (1) (2017)
James E. Smith
Efficient digital neurons for large scale cortical architectures. ISCA (2014)
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith
A mechanistic performance model for superscalar out-of-order processors. ACM Trans. Comput. Syst. 27 (2) (2009)
Stijn Eyerman, Lieven Eeckhout, James E. Smith
Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis. HiPEAC (2008)
Nidhi Aggarwal, James E. Smith, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan
Implementing high availability memory with a duplication cache. MICRO (2008)
Nidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti, James E. Smith
Power-Efficient DRAM Speculation. HPCA (2008)
Kyle J. Nesbit, Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, James E. Smith
Multicore Resource Management. IEEE Micro 28 (3) (2008)
Kyle J. Nesbit, James Laudon, James E. Smith
Virtual private caches. ISCA (2007)
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith
Configurable isolation: building high availability systems with commodity multi-core processors. ISCA (2007)
Stijn Eyerman, Lieven Eeckhout, James E. Smith
Studying Compiler-Microarchitecture Interactions through Interval Analysis. PACT (2007)
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith
A Top-Down Approach to Architecting CPI Component Performance Counters. IEEE Micro 27 (1) (2007)
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith
Isolation in Commodity Multicore Processors. Computer 40 (6) (2007)
Tejas Karkhanis, James E. Smith
Automated design of application specific superscalar processors: an analytical approach. ISCA (2007)
Ashutosh S. Dhodapkar, James E. Smith
Tuning adaptive microarchitectures. Int. J. Embed. Syst. 2 (1/2) (2006)
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith
A performance counter architecture for computing accurate CPI components. ASPLOS (2006)
Jason F. Cantin, James E. Smith, Mikko H. Lipasti, Andreas Moshovos, Babak Falsafi
Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays. IEEE Micro 26 (1) (2006)
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E. Smith
An approach for implementing efficient superscalar CISC processors. HPCA (2006)
Shiliang Hu, James E. Smith
Reducing Startup Time in Co-Designed Virtual Machines. ISCA (2006)
Jason F. Cantin, Mikko H. Lipasti, James E. Smith
Stealth prefetching. ASPLOS (2006)
Stijn Eyerman, James E. Smith, Lieven Eeckhout
Characterizing the branch misprediction penalty. ISPASS (2006)
Kyle J. Nesbit, Nidhi Aggarwal, James Laudon, James E. Smith
Fair Queuing Memory Systems. MICRO (2006)
Joshua J. Yi, Lieven Eeckhout, David J. Lilja, Brad Calder, Lizy Kurian John, James E. Smith
The Future of Simulation: A Field of Dreams. Computer 39 (11) (2006)
Jason F. Cantin, Mikko H. Lipasti, James E. Smith
The Complexity of Verifying Memory Coherence and Consistency. IEEE Trans. Parallel Distributed Syst. 16 (7) (2005)
James E. Smith
A unified view of virtualization. VEE (2005)
Kyle J. Nesbit, James E. Smith
Data Cache Prefetching Using a Global History Buffer. IEEE Micro 25 (1) (2005)
Jason F. Cantin, Mikko H. Lipasti, James E. Smith
Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking. ISCA (2005)
Tejas Karkhanis, James E. Smith
A First-Order Superscalar Processor Model. ISCA (2004)
Brad Calder, Daniel Citron, Yale N. Patt, James E. Smith
The future of simulation: A field of dreams. ISPASS (2004)
Kyle J. Nesbit, Ashutosh S. Dhodapkar, James E. Smith
AC/DC: An Adaptive Data Cache Prefetcher. IEEE PACT (2004)
Kyle J. Nesbit, James E. Smith
Data Cache Prefetching Using a Global History Buffer. HPCA (2004)
Ashutosh S. Dhodapkar, James E. Smith
Tuning Reconfigurable Microarchitectures for Power Efficiency. IPDPS (2004)
James E. Smith
Some Real Observations on Virtual Machines. Asia-Pacific Computer Systems Architecture Conference (2004)
Shiliang Hu, James E. Smith
Using Dynamic Binary Translation to Fuse Dependent Instructions. CGO (2004)
Ho-Seop Kim, James E. Smith
Hardware Support for Control Transfers in Code Caches. MICRO (2003)
Ho-Seop Kim, James E. Smith
Dynamic Binary Translation for Accumulator-Oriented Architectures. CGO (2003)
Ashutosh S. Dhodapkar, James E. Smith
Comparing Program Phase Detection Techniques. MICRO (2003)
James E. Smith
Keynote: Is there anything more to learn about high performance processors? ICS (2003)
Jason F. Cantin, Mikko H. Lipasti, James E. Smith
The complexity of verifying memory coherence. SPAA (2003)
Lieven Eeckhout, Sébastien Nussbaum, James E. Smith, Koen De Bosschere
Statistical Simulation: Adding Efficiency to the Computer Designer's Toolbox. IEEE Micro 23 (5) (2003)
Ashutosh S. Dhodapkar, James E. Smith
Managing Multi-Configuration Hardware via Dynamic Working Set Analysis. ISCA (2002)
George Cai, Ashutosh S. Dhodapkar, James E. Smith
Integrated Performance, Power, and Thermal Modeling. J. Circuits Syst. Comput. 11 (6) (2002)
Sébastien Nussbaum, James E. Smith
Statistical Simulation of Symmetric Multiprocessor Systems. Annual Simulation Symposium (2002)
Ho-Seop Kim, James E. Smith
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing. ISCA (2002)
Pradip Bose, David M. Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. PACS (2002)
Tejas Karkhanis, James E. Smith, Pradip Bose
Saving energy with just in time instruction delivery. ISLPED (2002)
Sébastien Nussbaum, James E. Smith
Modeling Superscalar Processors via Statistical Simulation. IEEE PACT (2001)
James E. Smith
Instruction-Level Distributed Processing. Computer 34 (4) (2001)
Eric Rotenberg, James E. Smith
Control Independence in Trace Processors. J. Instr. Level Parallelism 2 (2000)
James E. Smith
Instruction Level Distributed Processing: Adapting to Future Technology. ISHPC (2000)
James E. Smith
Instruction Level Distributed Processing. HiPC (2000)
Quinn Jacobson, James E. Smith
Trace preconstruction. ISCA (2000)
Eric Rotenberg, Steve Bennett, James E. Smith
A Trace Cache Microarchitecture and Evaluation. IEEE Trans. Computers 48 (2) (1999)
Eric Rotenberg, Quinn Jacobson, James E. Smith
A Study of Control Independence in Superscalar Processors. HPCA (1999)
Quinn Jacobson, James E. Smith
Instruction Pre-Processing in Trace Processors. HPCA (1999)
Eric Rotenberg, James E. Smith
Control Independence in Trace Processors. MICRO (1999)
Yiannakis Sazeides, James E. Smith
Limits of Data Value Predictability. Int. J. Parallel Program. 27 (4) (1999)
James E. Smith
Retrospective: Decoupled Access/Execute Architectures. 25 Years ISCA: Retrospectives and Reprints (1998)
James E. Smith
Decoupled Access/Execute Computer Architectures. 25 Years ISCA: Retrospectives and Reprints (1998)
Yiannakis Sazeides, James E. Smith
Modeling Program Predictability. ISCA (1998)
James E. Smith
Retrospective: A Study of Branch Prediction Strategies. 25 Years ISCA: Retrospectives and Reprints (1998)
James E. Smith
Retrospective: Implementing Precise Interrupts in Pipelined Processors. 25 Years ISCA: Retrospectives and Reprints (1998)
Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith
Trace Processors. MICRO (1997)
Quinn Jacobson, Steve Bennett, Nikhil Sharma, James E. Smith
Control Flow Speculation in Multiscalar Processors. HPCA (1997)
Subbarao Palacharla, Norman P. Jouppi, James E. Smith
Complexity-Effective Superscalar Processors. ISCA (1997)
Yiannakis Sazeides, James E. Smith
The Predictability of Data Values. MICRO (1997)
Quinn Jacobson, Eric Rotenberg, James E. Smith
Path-Based Next Trace Prediction. MICRO (1997)
Yiannakis Sazeides, Stamatis Vassiliadis, James E. Smith
The Performance Potential of Data Dependence Speculation & Collapsing. MICRO (1996)
Erik Jacobsen, Eric Rotenberg, James E. Smith
Assigning Confidence to Conditional Branch Predictions. MICRO (1996)
Eric Rotenberg, Steve Bennett, James E. Smith
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. MICRO (1996)
James E. Smith, Shlomo Weiss
PowerPC 601 and Alpha 21064: A Tale of Two RISCs. Computer 27 (6) (1994)
Corinna G. Lee, James E. Smith
A Study of Partitioned Vector Register Files. SC (1992)
Shlomo Weiss, James E. Smith
A study of scalar compilation techniques for pipelined supercomputers. ACM Trans. Math. Softw. 16 (3) (1990)
D. L. Fowler, James E. Smith
An accurate, high speed implementation of division by reciprocal approximation. IEEE Symposium on Computer Arithmetic (1989)
James E. Smith
Dynamic Instruction Scheduling and the Astronautics ZS-1. Computer 22 (7) (1989)
James E. Smith, Gregory E. Dermer, B. D. Vanderwarn, S. D. Klinger, C. M. Rozewski, D. L. Fowler, K. R. Scidmore, James Laudon
The Astronautics ZS-1 processor. ICCD (1988)
James E. Smith
Characterizing Computer Performance with a Single Number. Commun. ACM 31 (10) (1988)
Shlomo Weiss, James E. Smith
A Study of Scalar Compilation Techniques for Pipelined Supercomputers. ASPLOS (1987)
James E. Smith, Gregory E. Dermer, B. D. Vanderwarn, S. D. Klinger, C. M. Rozewski, D. L. Fowler, K. R. Scidmore, James Laudon
The ZS-1 Central Processor. ASPLOS (1987)
James E. Smith, Shlomo Weiss, Nicholas Y. Pang
A Simulation Study of Decoupled Architecture Computers. IEEE Trans. Computers 35 (8) (1986)
Craig S. Holt, James E. Smith
Self-Diagnosis in Distributed Systems. IEEE Trans. Computers 34 (1) (1985)
Shlomo Weiss, James E. Smith
Instruction Issue Logic in Pipelined Supercomputers. IEEE Trans. Computers 33 (11) (1984)
James E. Smith
On Separable Unordered Codes. IEEE Trans. Computers 33 (8) (1984)
James E. Smith
Decoupled Access/Execute Computer Architectures ACM Trans. Comput. Syst. 2 (4) (1984)
Shlomo Weiss, James E. Smith
Instruction Issue Logic for Pipelined Supercomputers. ISCA (1984)
James E. Smith, Paklin Lam
A Theory of Totally Self-Checking System Design. IEEE Trans. Computers 32 (9) (1983)
Lionel Bening, Thomas A. Lane, Curtis R. Alexander, James E. Smith
Developments in logic network path delay analysis. DAC (1982)
James E. Smith
Decoupled access/execute computer architectures. ISCA (1982)
Craig S. Holt, James E. Smith
Diagnosis of Systems with Asymmetric Invalidation. IEEE Trans. Computers 30 (9) (1981)
James E. Smith
A Study of Branch Prediction Strategies. ISCA (1981)
James E. Smith
Measures of the Effectiveness of Fault Signature Analysis. IEEE Trans. Computers 29 (6) (1980)
James E. Smith
Detection of Faults in Programmable Logic Arrays. IEEE Trans. Computers 28 (11) (1979)
James E. Smith
Universal System Diagnosis Algorithms. IEEE Trans. Computers 28 (5) (1979)
James E. Smith
Comments on "Redundancy Testing in Combinational Networks". IEEE Trans. Computers 28 (3) (1979)
James E. Smith
On Necessary and Sufficient Conditions for Multiple Fault Undetectability. IEEE Trans. Computers 28 (10) (1979)
James E. Smith, Gernot Metze
Strongly Fault Secure Logic Networks. IEEE Trans. Computers 27 (6) (1978)
James E. Smith
On the Existence of Combinational Logic Circuits Exhibiting Multiple Redundancy. IEEE Trans. Computers 27 (12) (1978)