David H. Albonesi

Publication Activity (10 Years)

Years Active: 1994-2020
Publications (10 Years): 10

Top Topics

Predictive Control

Resource Management

Top Venues

Publications

Nitish Kumar Srivastava, Hanchen Jin, Shaden Smith, Hongbo Rong, David H. Albonesi, Zhiru Zhang
Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations. HPCA (2020)
Neeraj Kulkarni, Gonzalo Gonzalez-Pumariega, Amulya Khurana, Christine A. Shoemaker, Christina Delimitrou, David H. Albonesi
CuttleSys: Data-Driven Resource Management forInteractive Applications on Reconfigurable Multicores. CoRR (2020)
Nitish Kumar Srivastava, Hanchen Jin, Jie Liu, David H. Albonesi, Zhiru Zhang
MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product. MICRO (2020)
Neeraj Kulkarni, Gonzalo Gonzalez-Pumariega, Amulya Khurana, Christine A. Shoemaker, Christina Delimitrou, David H. Albonesi
CuttleSys: Data-Driven Resource Management for Interactive Services on Reconfigurable Multicores. MICRO (2020)
Nitish Kumar Srivastava, Hongbo Rong, Prithayan Barua, Guanyu Feng, Huanqi Cao, Zhiru Zhang, David H. Albonesi, Vivek Sarkar, Wenguang Chen, Paul Petersen, Geoff Lowney, Adam Herr, Christopher J. Hughes, Timothy G. Mattson, Pradeep Dubey
T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations. FCCM (2019)
Tayyar Rzayev, Saber Moradi, David H. Albonesi, Rajit Manohar
DeepRecon: Dynamically reconfigurable architecture for accelerating deep neural networks. IJCNN (2017)
Tayyar Rzayev, David H. Albonesi, François Guimbretière, Rajit Manohar, Jaeyeon Kihm
Toolbox for exploration of energy-efficient event processors for human-computer interaction. ISPASS (2017)
Abhinandan Majumdar, Leonardo Piga, Indrani Paul, Joseph L. Greathouse, Wei Huang, David H. Albonesi
Dynamic GPGPU Power Management Using Adaptive Model Predictive Control. HPCA (2017)
Abhinandan Majumdar, Zhiru Zhang, David H. Albonesi
Characterizing the Benefits and Limitations of Smart Building Meeting Room Scheduling. ICCPS (2016)
David H. Albonesi
2015 International Symposium on Computer Architecture Influential Paper Award. IEEE Micro 36 (6) (2016)
Abhinandan Majumdar, Jason L. Setter, Justin R. Dobbs, Brandon M. Hencey, David H. Albonesi
Energy-comfort optimization using discomfort history and probabilistic occupancy prediction. IGCC (2014)
Paula Petrica, Adam M. Izraelevitz, David H. Albonesi, Christine A. Shoemaker
Flicker: a dynamically adaptive architecture for power limited multicore systems. ISCA (2013)
Abhinandan Majumdar, David H. Albonesi, Pradip Bose
Energy-aware meeting scheduling algorithms for smart buildings. BuildSys@SenSys (2012)
Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo
A phase adaptive cache hierarchy for SMT processors. Microprocess. Microsystems 35 (8) (2011)
Mark J. Cianchetti, David H. Albonesi
A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors. ACM J. Emerg. Technol. Comput. Syst. 7 (2) (2011)
Matthew A. Watkins, David H. Albonesi
ReMAP: A Reconfigurable Architecture for Chip Multiprocessors. IEEE Micro 31 (1) (2011)
David H. Albonesi
Future Directions in Computer Architecture Research. IEEE Micro 30 (3) (2010)
Matthew A. Watkins, David H. Albonesi
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture. MICRO (2010)
Jonathan A. Winter, David H. Albonesi, Christine A. Shoemaker
Scalable thread scheduling and global power management for heterogeneous many-core architectures. PACT (2010)
Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo
Adaptive Cache Memories for SMT Processors. DSD (2010)
Matthew A. Watkins, David H. Albonesi
Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors. PACT (2010)
David H. Albonesi
Moving Forward. IEEE Micro 30 (6) (2010)
David H. Albonesi
From the Editor in Chief: Welcome A-Board. IEEE Micro 29 (5) (2009)
Mark J. Cianchetti, Joseph C. Kerekes, David H. Albonesi
Phastlane: a rapid transit optical routing network. ISCA (2009)
David H. Albonesi
Changes Ahead. IEEE Micro 28 (5) (2008)
Jonathan A. Winter, David H. Albonesi
Addressing thermal nonuniformity in SMT workloads. ACM Trans. Archit. Code Optim. 5 (1) (2008)
Jonathan A. Winter, David H. Albonesi
Scheduling algorithms for unpredictably heterogeneous CMP architectures. DSN (2008)
Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi
Shared reconfigurable architectures for CMPS. FPL (2008)
David H. Albonesi
Editor in Chief's Message: Truly "hot" chips - Do we still care? IEEE Micro 27 (2) (2007)
Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman
On-chip optical interconnect for reduced delay uncertainty. Nano-Net (2007)
David H. Albonesi
Standing on Solid Ground. IEEE Micro 27 (1) (2007)
David H. Albonesi
More Hot Stuff. IEEE Micro 27 (3) (2007)
David H. Albonesi
Productive and Healthy Debate. IEEE Micro 27 (6) (2007)
Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman
Predictions of CMOS compatible on-chip optical interconnect. Integr. 40 (4) (2007)
David H. Albonesi
Mixing It Up. IEEE Micro 27 (4) (2007)
Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. HiPEAC (2007)
Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi
On-Chip Optical Technology in Future Bus-Based Multicore Designs. IEEE Micro 27 (1) (2007)
Sonia López, Steven G. Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares
Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors. PACT (2007)
Yongkang Zhu, David H. Albonesi
Localized microarchitecture-level voltage management. ISCAS (2006)
Ali El-Moursy, Rajeev Garg, David H. Albonesi, Sandhya Dwarkadas
Compatible phase co-scheduling on a CMP of multi-threaded processors. IPDPS (2006)
Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors. MICRO (2006)
Yongkang Zhu, David H. Albonesi
Synergistic temperature and energy management in GALS processor architectures. ISLPED (2006)
Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi
Predictions of CMOS compatible on-chip optical interconnect. SLIP (2005)
Yongkang Zhu, David H. Albonesi, Alper Buyuktosunoglu
A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity. ISPASS (2005)
Gregory J. Briggs, Edwin J. Tan, Nicholas A. Nelson, David H. Albonesi
QUILT: a GUI-based integrated circuit floorplanning environment for computer architecture research and education. WCAE@ISCA (2005)
Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi
Electrical and optical on-chip interconnects in scaled microprocessors. ISCAS (3) (2005)
Ali El-Moursy, Rajeev Garg, David H. Albonesi, Sandhya Dwarkadas
Partitioning Multi-Threaded Processors with a Large Number of Threads. ISPASS (2005)
M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, David H. Albonesi
Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance. IEEE PACT (2005)
M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, David H. Albonesi
Power-Efficient Error Tolerance in Chip Multiprocessors. IEEE Micro 25 (6) (2005)
Wanli Liu, David H. Albonesi, John Gostomski, Lloyd Palum, Dave Hinterberger, Rick Wanzenried, Mark Indovina
An Evaluation of a Configurable Vliw Microarchitecture for Embedded Dsp Applications. J. Circuits Syst. Comput. 13 (6) (2004)
Yongkang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding, David H. Albonesi
The Energy Impact of Aggressive Loop Fusion. IEEE PACT (2004)
Steven G. Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott
Dynamically Trading Frequency for Complexity in a GALS Microprocessor. MICRO (2004)
David H. Albonesi
Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences. IEEE Micro 24 (6) (2004)
Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas
Hiding Synchronization Delays in a GALS Processor Microarchitecture. ASYNC (2004)
Grigorios Magklis, Greg Semeraro, David H. Albonesi, Steve Dropsho, Sandhya Dwarkadas, Michael L. Scott
Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor. IEEE Micro 23 (6) (2003)
David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster
Dynamically Tuning Processor Resources with Adaptive Processing. Computer 36 (12) (2003)
Pradip Bose, David H. Albonesi, Diana Marculescu
Guest Editors' Introduction: Power and Complexity Aware Design. IEEE Micro 23 (5) (2003)
Ali El-Moursy, David H. Albonesi
Front-End Policies for Improved Issue Efficiency in SMT Processors. HPCA (2003)
Lei Chen, Steve Dropsho, David H. Albonesi
Dynamic Data Dependence Tracking and its Application to Branch Prediction. HPCA (2003)
Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose
Energy Efficient Co-Adaptive Instruction Fetch and Issue. ISCA (2003)
Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
A Dynamically Tunable Memory Hierarchy. IEEE Trans. Computers 52 (10) (2003)
Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors. ISCA (2003)
Grigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, Steve Dropsho
Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor. ISCA (2003)
Greg Semeraro, David H. Albonesi, Steve Dropsho, Grigorios Magklis, Sandhya Dwarkadas, Michael L. Scott
Dynamic frequency and voltage control for a multiple clock domain microarchitecture. MICRO (2002)
Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster
Tradeoffs in power-efficient issue queue design. ISLPED (2002)
Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott
Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. HPCA (2002)
Pradip Bose, David M. Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. PACS (2002)
Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigorios Magklis, Michael L. Scott
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. IEEE PACT (2002)
Wael El-Essawy, David H. Albonesi, Balaram Sinharoy
A microarchitectural-level step-power analysis tool. ISLPED (2002)
Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman
Managing static leakage energy in microprocessor functional units. MICRO (2002)
Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David M. Brooks, Pradip Bose, Peter W. Cook
A circuit level implementation of an adaptive issue queue for power-aware microprocessors. ACM Great Lakes Symposium on VLSI (2001)
Brian W. Curran, Mary Gifaldi, Jason Martin, Alper Buyuktosunoglu, Martin Margala, David H. Albonesi
Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors. VLSI-SOC (2001)
Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
Dynamically allocating processor resources between nearby and distant ILP. ISCA (2001)
Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
Reducing the complexity of the register file in dynamic superscalar processors. MICRO (2001)
David H. Albonesi
Selective Cache Ways: On-Demand Cache Resource Allocation. J. Instr. Level Parallelism 2 (2000)
Bingxiong Xu, David H. Albonesi
Runtime Reconfiguration Techniques for Efficient General-Purpose Computation. IEEE Des. Test Comput. 17 (1) (2000)
Alper Buyuktosunoglu, Stanley Schuster, David M. Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi
An Adaptive Issue Queue for Reduced Power at High Performance. PACS (2000)
Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. MICRO (2000)
David H. Albonesi
An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures. VLSI (1999)
David H. Albonesi
Selective Cache Ways: On-Demand Cache Resource Allocation. MICRO (1999)
David H. Albonesi, Israel Koren
STATS: A framework for microprocessor and system-level design space exploration. J. Syst. Archit. 45 (12-13) (1999)
David H. Albonesi
Dynamic IPC/Clock Rate Optimization. ISCA (1998)
David H. Albonesi, Israel Koren
Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue, Microprocessor-Based Systems. IEEE PACT (1997)
David H. Albonesi, Israel Koren
A Mean Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating Techniques. Int. J. Parallel Program. 24 (3) (1996)
David H. Albonesi, Israel Koren
An analytical model of high performance superscalar-based multiprocessors. PACT (1995)
David H. Albonesi, Israel Koren
Architecture and technology tradeoffs in the design of next-generation multiprocessor servers. SPDP (1995)
David H. Albonesi, Israel Koren
Tradeoffs in the Design of Single Chip Multiprocessors. IFIP PACT (1994)