Martin Margala

ORCID

Publication Activity (10 Years)

Years Active: 1994-2024
Publications (10 Years): 53

Top Venues

Publications

Alaaddin Goktug Ayar, Abdullah Sahruri, Sercan Aygun, Mehran Shoushtari Moghadam, M. Hassan Najafi, Martin Margala
Detecting Vulnerability in Hardware Description Languages: Opcode Language Processing. IEEE Embed. Syst. Lett. 16 (2) (2024)
Manisha Guduri, Chinmay Chakraborty, V. Uma Maheswari, Martin Margala
Blockchain-Based Federated Learning Technique for Privacy Preservation and Security of Smart Electronic Health Records. IEEE Trans. Consumer Electron. 70 (1) (2024)
Jeetendra Kumar, Rashmi Gupta, Suvarna Sharma, Tulika Chakrabarti, Prasun Chakrabarti, Martin Margala
IoT-Enabled Advanced Water Quality Monitoring System for Pond Management and Environmental Conservation. IEEE Access 12 (2024)
P. Dileep Kumar Reddy, Martin Margala, S. Siva Shankar, Prasun Chakrabarti
Early fire danger monitoring system in smart cities using optimization-based deep learning techniques with artificial intelligence. J. Reliab. Intell. Environ. 10 (2) (2024)
Sudheer Mangalampalli, Syed Shakeel Hashmi, Amit Gupta, Ganesh Reddy Karri, K. Varada Rajkumar, Tulika Chakrabarti, Prasun Chakrabarti, Martin Margala
Multi Objective Prioritized Workflow Scheduling Using Deep Reinforcement Based Learning in Cloud Computing. IEEE Access 12 (2024)
Abdullah Sahruri, Martin Margala, Ugur Çilingiroglu
HiCTL: High Fan-in Differential Capacitive-Threshold-Logic Gate Implementation With an Offset-Compensated Comparator. ISQED (2024)
G. Nagarajan, Martin Margala, S. Siva Shankar, Prasun Chakrabarti, R. I. Minu
A trust-centric approach to intrusion detection in edge networks for medical internet of thing Ecosystems. Comput. Electr. Eng. 115 (2024)
Alaaddin Goktug Ayar, Sercan Aygun, M. Hassan Najafi, Martin Margala
Word2HyperVec: From Word Embeddings to Hypervectors for Hyperdimensional Computing. ACM Great Lakes Symposium on VLSI (2024)
Sudheer Mangalampalli, Sangram Keshari Swain, Tulika Chakrabarti, Prasun Chakrabarti, Ganesh Reddy Karri, Martin Margala, Bhuvan Unhelkar, Sivaneasan Bala Krishnan
Prioritized Task-Scheduling Algorithm in Cloud Computing Using Cat Swarm Optimization. Sensors 23 (13) (2023)
Sudheer Mangalampalli, Ganesh Reddy Karri, Amit Gupta, Tulika Chakrabarti, Sri Hari Nallamala, Prasun Chakrabarti, Bhuvan Unhelkar, Martin Margala
Fault-Tolerant Trust-Based Task Scheduling Algorithm Using Harris Hawks Optimization in Cloud Computing. Sensors 23 (18) (2023)
Shachi Khadilkar, Ahmed Sanaullah, Martin Margala
Quantifying the Gap between Open-Source and Vendor FPGA Place and Route Tools. HPEC (2023)
Mohamed El-Hadedy, Russell Hua, Kazutomo Yoshii, Wen-Mei Hwu, Martin Margala
RECO-LFSR: Reconfigurable Low-power Cryptographic processor based on LFSR for Trusted IoT platforms. ISQED (2023)
Manisha G, Amit Krishna Dwivedi, Uma Maheshwari V, Prasun Chakrabarti, Martin Margala
Optimum Supply Voltage for High Gain Amplifier in Telemetry Circuitry for Ultra-Low Power Implantable Cardiac Pacemaker. NEWCAS (2023)
Mohamed El-Hadedy, Russell Hua, Shahzman Saqib, Kazutomo Yoshii, Wen-Mei Hwu, Martin Margala
BLTESTI: Benchmarking Lightweight TinyJAMBU on Embedded Systems for Trusted IoT. SOCC (2023)
Uchechukwu Leo Udeji, Martin Margala
FPGA Implementation of Addition-based CORDIC-SNN With Izhikevich Neurons. SOCC (2022)
Shachi Khadilkar, Martin Margala
Optimizing open-source FPGA CAD tools. HPEC (2022)
Sharath Patil, Bhanu Singh, Raunak Borwankar, Martin Margala
Novel Pulse Detection System Using Differentiation: Prototyping and Experimental Results. NEWCAS (2022)
Sharath Patil, Bhanu Singh, Raunak Borwankar, Martin Margala
Novel Pulse Detection System Using Differentiation: Optical Experimental Results. SOCC (2022)
Philip Colangelo, Oren Segal, Alexander Speicher, Martin Margala
AutoML for Multilayer Perceptron and FPGA Co-design. CoRR (2020)
Philip Colangelo, Oren Segal, Alexander Speicher, Martin Margala
Automated Hardware and Neural Network Architecture co-design of FPGA accelerators using multi-objective Neural Architecture Search. ICCE-Berlin (2020)
Sharath Patil, Bhanu Singh, Darrell Livezey, Saad Ahmad, Martin Margala
Functional Safety of a Lidar Sensor System. MWSCAS (2020)
Philip Colangelo, Oren Segal, Alexander Speicher, Martin Margala
AutoML for Multilayer Perceptron and FPGA Co-design. SoCC (2020)
Mohamed El-Hadedy, Martin Margala, Sergiu Mosanu, Danilo Gligoroski, Jinjun Xiong, Wen-Mei Hwu
Micro - GAGE: A Low-power Compact GAGE Hash Function Processor for IoT Applications. ICECS (2020)
Philip Colangelo, Shayan Sengupta, Martin Margala
Sparse Persistent GEMM Accelerator using OpenCL for Intel FPGAs. ISCAS (2020)
Wim Vanderbauwhede, Sven-Bodo Scholz, Martin Margala
FPGAs for Domain Experts. Int. J. Reconfigurable Comput. 2020 (2020)
Sharath Patil, Volodymyr Seliuchenko, Darrell Livezey, Saad Ahmad, Bhanu Singh, Martin Margala
Echo Detection Using Differentiation for Compact LIDAR Implementation. MWSCAS (2019)
Philip Colangelo, Oren Segal, Alexander Speicher, Martin Margala
Evolutionary Cell Aided Design for Neural Network Architectures. CoRR (2019)
Philip Colangelo, Oren Segal, Alexander Speicher, Martin Margala
Artificial Neural Network and Accelerator Co-design using Evolutionary Algorithms. HPEC (2019)
Huan Wang, Jean-François Millithaler, Martin Margala, Ronald W. Knepper
THz Ballistic Deflection Transistor Travelling Wave Amplifier Design with THz Ring Hybrid Coupler. NEWCAS (2018)
Huan Wang, Jean-François Millithaler, Ronald W. Knepper, Martin Margala
Terahertz travelling wave amplifier design using Ballistic Deflection Transistor. ISQED (2018)
Huan Wang, Ronald W. Knepper, Jean-François Millithaler, Martin Margala
A Novel Terahertz Ballistic Deflection Transistor Travelling Wave Amplifier System. IEEE Trans. Circuits Syst. II Express Briefs (10) (2018)
Aydin Dirican, Cagatay Ozmen, Martin Margala
A droop measurement built-in self-test circuit for digital low-dropout regulators. ISQED (2018)
Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs. FCCM (2018)
Philip Colangelo, Nasibeh Nasiri, Asit K. Mishra, Eriko Nurvitadhi, Martin Margala, Kevin Nealis
Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs. CoRR (2018)
Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only). FPGA (2018)
Hieu Nguyen, Rod Comer, Phuc Pham, Martin Margala
5-Gb/s linear re-driver in 180 nm CMOS technology. Microelectron. J. 82 (2018)
Aydin Dirican, Cagatay Ozmen, Martin Margala
Leakage-Aware Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators. J. Electron. Test. 34 (4) (2018)
Philip Colangelo, Randy Huang, Enno Lübbers, Martin Margala, Kevin Nealis
Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA. FCCM (2017)
Cagatay Ozmen, Aydin Dirican, Hieu Nguyen, Martin Margala
ROIC Design for a 10k Pixel Photoresistive Image Sensor with On-Chip Calibration. NGCAS (2017)
Philip Colangelo, Enno Lübbers, Randy Huang, Martin Margala, Kevin Nealis
Application of convolutional neural networks on Intel® Xeon® processor with integrated FPGA. HPEC (2017)
Pilin Junsangsri, Fabrizio Lombardi, Salin Junsangsri, Martin Margala
Design of a Low-Power Non-Volatile Programmable Inverter Cell for COGRE-based Circuits. ACM Great Lakes Symposium on VLSI (2017)
Poorna Marthi, Nazir Hossain, Huan Wang, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González
A high performance Full Adder based on Ballistic Deflection Transistor technology. ISCAS (2017)
Mohamed El-Hadedy, Xinfei Guo, Martin Margala, Mircea R. Stan, Kevin Skadron
Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems. J. Signal Process. Syst. 88 (2) (2017)
Cagatay Ozmen, Aydin Dirican, Hieu Nguyen, Martin Margala
Sensitivity improvement of a photoresistive image sensor with novel programmable dual element readout and calibration method. MWSCAS (2017)
Cagatay Ozmen, Aydin Dirican, Hieu Nguyen, Martin Margala
Column-wise ROIC design with on-chip calibration for photoresistive image sensor. ECCTD (2017)
Poorna Marthi, Nazir Hossain, Huan Wang, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González
Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2016)
Zhuo Qian, Martin Margala
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units. IEEE Trans. Very Large Scale Integr. Syst. 24 (9) (2016)
Nasibeh Nasiri, Philip Colangelo, Oren Segal, Martin Margala, Wim Vanderbauwhede
Document classification systems in heterogeneous computing environments. PATMOS (2016)
Poorna Marthi, Sheikh Rufsan Reza, Nazir Hossain, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González
Modeling and Study of Two-BDT-Nanostructure based Sequential Logic Circuits. ACM Great Lakes Symposium on VLSI (2016)
Hieu Nguyen, Cagatay Ozmen, Aydin Dirican, Nurettin Tan, Martin Margala
A CMOS Ripple Detector for Voltage Regulator Testing. J. Electron. Test. 32 (2) (2016)
Oren Segal, Martin Margala
Exploring the performance benefits of heterogeneity and reconfigurable architectures in a commodity cloud. HPCS (2016)
Oren Segal, Nasibeh Nasiri, Martin Margala
A Foray into Efficient Mapping of Algorithms to Hardware Platforms on Heterogeneous Systems. CoRR (2016)
Poorna Marthi, Nazir Hossain, Jean-François Millithaler, Martin Margala
A new level sensitive D Latch using Ballistic nanodevices. ISCAS (2016)
Oren Segal, Philip Colangelo, Nasibeh Nasiri, Zhuo Qian, Martin Margala
Aparapi-UCores: A high level programming framework for unconventional cores. HPEC (2015)
Cagatay Ozmen, Aydin Dirican, Nurettin Tan, Hieu Nguyen, Martin Margala
A CMOS ripple detector for integrated voltage regulator testing. DFTS (2015)
Nasibeh Nasiri, Oren Segal, Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti
High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only). FPGA (2015)
Oren Segal, Philip Colangelo, Nasibeh Nasiri, Zhuo Qian, Martin Margala
SparkCL: A Unified Programming Framework for Accelerators on Heterogeneous Clusters. CoRR (2015)
Cagatay Ozmen, Aydin Dirican, Nurettin Tan, Hieu Nguyen, Martin Margala
A CMOS ripple detector for integrated voltage regulator testing. MWSCAS (2015)
Zhuo Qian, Martin Margala
A Novel Coefficient Address Generation Algorithm for Split-Radix FFT (Abstract Only). FPGA (2015)
Zhuo Qian, Nasibeh Nasiri, Oren Segal, Martin Margala
FPGA implementation of low-power split-radix FFT processors. FPL (2014)
Zhuo Qian, Martin Margala
A novel low-power and in-place split-radix FFT processor. ACM Great Lakes Symposium on VLSI (2014)
Oren Segal, Martin Margala, Sai Rahul Chalamalasetti, Mitch Wright
High level programming framework for FPGAs in the data center. FPL (2014)
Oren Segal, Martin Margala, Sai Rahul Chalamalasetti, Mitch Wright
High Level Programming for Heterogeneous Architectures. CoRR (2014)
Oren Segal, Nasibeh Nasiri, Martin Margala, Wim Vanderbauwhede
High level programming of FPGAs for HPC and data centric applications. HPEC (2014)
Nasibeh Nasiri, Oren Segal, Martin Margala
Modified fused multiply-accumulate chained unit. MWSCAS (2014)
Zhuo Qian, Martin Margala
Low power RAM-based hierarchical CAM on FPGA. ReConFig (2014)
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede
Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications. IEEE Trans. Very Large Scale Integr. Syst. 21 (7) (2013)
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede
Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems. IEEE Trans. Very Large Scale Integr. Syst. 21 (10) (2013)
Wim Vanderbauwhede, Anton Frolov, Sai Rahul Chalamalasetti, Martin Margala
A hybrid CPU-FPGA system for high throughput (10Gb/s) streaming document classification. SIGARCH Comput. Archit. News 41 (5) (2013)
Wim Vanderbauwhede, Anton Frolov, Leif Azzopardi, Sai Rahul Chalamalasetti, Martin Margala
High throughput filtering using FPGA-acceleration. CIKM (2013)
Sai Rahul Chalamalasetti, Kevin T. Lim, Mitch Wright, Alvin AuYoung, Parthasarathy Ranganathan, Martin Margala
An FPGA memcached appliance. FPGA (2013)
Samed Maltabas, Osman Kubilay Ekekon, Kemal Kulovic, Anne Meixner, Martin Margala
An IDDQ BIST approach to characterize phase-locked loop parameters. VTS (2013)
Samed Maltabas, Kemal Kulovic, Martin Margala
Novel Practical Built-in Current Sensors. J. Electron. Test. 28 (5) (2012)
Kemal Kulovic, Martin Margala
Time-Based Embedded Test Instrument with Concurrent Voltage Measurement Capability. J. Electron. Test. 28 (5) (2012)
Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Martin Margala
Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application. Int. J. Reconfigurable Comput. 2012 (2012)
Kemal Kulovic, Samed Maltabas, Martin Margala
Design-for-test methodologies for current tests in Analog/Mixed-Signal Power SOCs. MWSCAS (2012)
Sohan Purohit, Martin Margala
Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance. IEEE Trans. Very Large Scale Integr. Syst. 20 (7) (2012)
Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede, Mitch Wright, Parthasarathy Ranganathan
Evaluating FPGA-acceleration for real-time unstructured search. ISPASS (2012)
Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala
A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks. HPCS (2011)
Osman Kubilay Ekekon, Samed Maltabas, Martin Margala
A multi-GHz PLL Built-In jitter extraction circuit for deep submicron technologies. ECCTD (2011)
Vikas Kaushal, Ignacio Iñiguez-de-la-Torre, Martin Margala
Topology impact on the room temperature performance of THz-range ballistic deflection transistors. ACM Great Lakes Symposium on VLSI (2010)
Osman Kubilay Ekekon, Samed Maltabas, Martin Margala, Ugur Çilingiroglu
Power minimization methodology for VCTL topologies. SoCC (2010)
Mohamed El-Hadedy, Martin Margala, Danilo Gligoroski, Svein J. Knapskog
Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA Platform. ReConFig (2010)
Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede
Radiation-Hardened Reconfigurable Array With Instruction Roll-Back. IEEE Embed. Syst. Lett. 2 (4) (2010)
Mohamed El-Hadedy, Sohan Purohit, Martin Margala, Svein J. Knapskog
Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems. AHS (2010)
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala
Design of self correcting radiation hardened digital circuits using decoupled ground bus. ACM Great Lakes Symposium on VLSI (2010)
Sohan Purohit, Marco Lanuzza, Martin Margala
Design Space Exploration of Split-Path Data Driven Dynamic Full Adder. J. Low Power Electron. 6 (4) (2010)
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala
Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths. AHS (2010)
Osman Kubilay Ekekon, Samed Maltabas, Martin Margala
Novel programmable built-in current-sensor for analog, digital and mixed-signal circuits. ISCAS (2010)
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit
A C++-embedded Domain-Specific Language for programming the MORA soft processor array. ASAP (2010)
Sohan Purohit, David Harrington, Martin Margala
An area efficient design methodology for SEU tolerant digital circuits. ISCAS (2010)
Samed Maltabas, Osman Kubilay Ekekon, Martin Margala
A new built-in IDDQ testing method using programmable BICS. ETS (2010)
Mohamed El-Hadedy, Martin Margala, Danilo Gligoroski, Svein J. Knapskog
Resource-efficient implementation of Blue Midnight Wish-256 hash function on Xilinx FPGA platform. IAS (2010)
Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede
MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor. AHS (2009)
Samed Maltabas, Martin Margala, Ugur Çilingiroglu
Varicap threshold logic. ACM Great Lakes Symposium on VLSI (2009)
Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. VLSI Design (2009)
Vikas Kaushal, Quentin Diduck, Martin Margala
Study of leakage current mechanisms in ballistic deflection transistors. ACM Great Lakes Symposium on VLSI (2009)
David Wolpert, Hiroshi Irie, Roman Sobolewski, Paul Ampadu, Quentin Diduck, Martin Margala
Ballistic Deflection Transistors and the Emerging Nanoscale Era. ISCAS (2009)
Sai Rahul Chalamalasetti, Wim Vanderbauwhede, Sohan Purohit, Martin Margala
A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model. FPL (2009)
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor. ERSA (2009)

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Publication Activity (10 Years)

Top Topics

Top Venues

Martin Margala