Sai Rahul Chalamalasetti

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 17

Top Topics

Incremental Updates

Machine Learning

Neural Network Training

Document Classification

Top Venues

Publications

Pedro Bruel, Sai Rahul Chalamalasetti, Aditya Dhakal, Eitan Frachtenberg, Ninad Hogade, Rolando Pablo Hong Enriquez, Alok Mishra, Dejan Milojicic, Pavana Prakash, Gourav Rattihalli
Predicting Heterogeneity and Serverless Principles of Converged High-Performance Computing, Artificial Intelligence, and Workflows. Computer 57 (1) (2024)
Tobias Pfandzelter, Aditya Dhakal, Eitan Frachtenberg, Sai Rahul Chalamalasetti, Darel Emmot, Ninad Hogade, Rolando Pablo Hong Enriquez, Gourav Rattihalli, David Bermbach, Dejan S. Milojicic
Kernel-as-a-Service: A Serverless Programming Model for Heterogeneous Hardware Accelerators. Middleware (2023)
Sitao Huang, Aayush Ankit, Plínio Silveira, Rodrigo Antunes, Sai Rahul Chalamalasetti, Izzat El Hajj, Dong Eun Kim, Glaucimar Aguiar, Pedro Bruel, Sergey Serebryakov, Cong Xu, Can Li, Paolo Faraboschi, John Paul Strachan, Deming Chen, Kaushik Roy, Wen-Mei W. Hwu, Dejan S. Milojicic
Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators. ASP-DAC (2021)
Plínio Silveira, César Augusto Fonticielha De Rose, Avelino Francisco Zorzo, Miguel Gomes Xavier, Dejan S. Milojicic, Sai Rahul Chalamalasetti, Sergey Serebryakov
Resource Sharing and Security Implications on Machine Learning Inference Accelerators. COMPSAC (2021)
Sitao Huang, Kun Wu, Sai Rahul Chalamalasetti, Izzat El Hajj, Cong Xu, Paolo Faraboschi, Deming Chen
A Python-based High-Level Programming Flow for CPU-FPGA Heterogeneous Systems : (Invited Paper). PEHC@SC (2021)
Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Sapan Agarwal, Matthew J. Marinella, Martin Foltin, John Paul Strachan, Dejan S. Milojicic, Wen-Mei Hwu, Kaushik Roy
PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM. IEEE Trans. Computers 69 (8) (2020)
Martin Foltin, Glaucimar Aguiar, Rodrigo Antunes, Plínio Silveira, Gustavo Knuppe, Joao Ambrosi, Soumitra Chatterjee, Jitendra Onkar Kolhe, Sunil Lakshiminarashimha, Dejan S. Milojicic, John Paul Strachan, Craig Warner, Amit Sharma, Eddie Lee, Sai Rahul Chalamalasetti, Chris Brueggen, Charles Williams, Nathaniel Jansen, Felipe Saenz, Luis Federico Li
FPGA Demonstrator of a Programmable Ultra-Efficient Memristor-Based Machine Learning Inference Accelerator. ICRC (2019)
Sitao Huang, Li-Wen Chang, Izzat El Hajj, Simon Garcia De Gonzalo, Juan Gómez-Luna, Sai Rahul Chalamalasetti, Mohamed El-Hadedy, Dejan S. Milojicic, Onur Mutlu, Deming Chen, Wen-Mei W. Hwu
Analysis and Modeling of Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures. ICPE (2019)
Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Sapan Agarwal, Matthew J. Marinella, Martin Foltin, John Paul Strachan, Dejan S. Milojicic, Wen-Mei W. Hwu, Kaushik Roy
PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-efficient ReRAM. CoRR (2019)
Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Geoffrey Ndu, Martin Foltin, R. Stanley Williams, Paolo Faraboschi, Wen-mei W. Hwu, John Paul Strachan, Kaushik Roy, Dejan S. Milojicic
PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference. ASPLOS (2019)
Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Geoffrey Ndu, Martin Foltin, R. Stanley Williams, Paolo Faraboschi, Wen-Mei Hwu, John Paul Strachan, Kaushik Roy, Dejan S. Milojicic
PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference. CoRR (2019)
Joao Ambrosi, Aayush Ankit, Rodrigo Antunes, Sai Rahul Chalamalasetti, Soumitra Chatterjee, Izzat El Hajj, Guilherme Fachini, Paolo Faraboschi, Martin Foltin, Sitao Huang, Wen-Mei Hwu, Gustavo Knuppe, Sunil Vishwanathpur Lakshminarasimha, Dejan S. Milojicic, Mohan Parthasarathy, Filipe Ribeiro, Lucas Rosa, Kaushik Roy, Plínio Silveira, John Paul Strachan
Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning. ICRC (2018)
Catherine E. Graves, Wen Ma, Xia Sheng, Brent Buchanan, Le Zheng, Sity Lam, Xuema Li, Sai Rahul Chalamalasetti, Lennie Kiyama, Martin Foltin, John Paul Strachan, Matthew P. Hardy
Regular Expression Matching with Memristor TCAMs for Network Security. NANOARCH (2018)
Catherine E. Graves, Wen Ma, Xia Sheng, Brent Buchanan, Le Zheng, Sity Lam, Xuema Li, Sai Rahul Chalamalasetti, Lennie Kiyama, Martin Foltin, Matthew P. Hardy, John Paul Strachan
Regular Expression Matching with Memristor TCAMs. ICRC (2018)
Pedro Bruel, Sai Rahul Chalamalasetti, Chris I. Dalton, Izzat El Hajj, Alfredo Goldman, Catherine Graves, Wen-Mei W. Hwu, Phil Laplante, Dejan S. Milojicic, Geoffrey Ndu, John Paul Strachan
Generalize or Die: Operating Systems Support for Memristor-Based Accelerators. ICRC (2017)
Pedro Bruel, Alfredo Goldman, Sai Rahul Chalamalasetti, Dejan S. Milojicic
Autotuning high-level synthesis for FPGAs using OpenTuner and LegUp. ReConFig (2017)
Nasibeh Nasiri, Oren Segal, Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti
High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only). FPGA (2015)
Oren Segal, Martin Margala, Sai Rahul Chalamalasetti, Mitch Wright
High level programming framework for FPGAs in the data center. FPL (2014)
Oren Segal, Martin Margala, Sai Rahul Chalamalasetti, Mitch Wright
High Level Programming for Heterogeneous Architectures. CoRR (2014)
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede
Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications. IEEE Trans. Very Large Scale Integr. Syst. 21 (7) (2013)
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede
Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems. IEEE Trans. Very Large Scale Integr. Syst. 21 (10) (2013)
Wim Vanderbauwhede, Anton Frolov, Sai Rahul Chalamalasetti, Martin Margala
A hybrid CPU-FPGA system for high throughput (10Gb/s) streaming document classification. SIGARCH Comput. Archit. News 41 (5) (2013)
Wim Vanderbauwhede, Anton Frolov, Leif Azzopardi, Sai Rahul Chalamalasetti, Martin Margala
High throughput filtering using FPGA-acceleration. CIKM (2013)
Sai Rahul Chalamalasetti, Kevin T. Lim, Mitch Wright, Alvin AuYoung, Parthasarathy Ranganathan, Martin Margala
An FPGA memcached appliance. FPGA (2013)
Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Martin Margala
Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application. Int. J. Reconfigurable Comput. 2012 (2012)
Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede, Mitch Wright, Parthasarathy Ranganathan
Evaluating FPGA-acceleration for real-time unstructured search. ISPASS (2012)
Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala
A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks. HPCS (2011)
Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede
Radiation-Hardened Reconfigurable Array With Instruction Roll-Back. IEEE Embed. Syst. Lett. 2 (4) (2010)
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala
Design of self correcting radiation hardened digital circuits using decoupled ground bus. ACM Great Lakes Symposium on VLSI (2010)
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala
Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths. AHS (2010)
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit
A C++-embedded Domain-Specific Language for programming the MORA soft processor array. ASAP (2010)
Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede
MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor. AHS (2009)
Sai Rahul Chalamalasetti, Wim Vanderbauwhede, Sohan Purohit, Martin Margala
A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model. FPL (2009)
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor. ERSA (2009)
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala
A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic. ACM Great Lakes Symposium on VLSI (2009)
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello
Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices. ReConFig (2008)
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello
Power/throughput/area efficient PIM-based reconfigurable array for parallel processing. SoCC (2008)