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Sohan Purohit
Publication Activity (10 Years)
Years Active: 2008-2014
Publications (10 Years): 0
Top Topics
Efficient Implementation
Digital Computer
Bit Parallel
Computation Intensive
Top Venues
IEEE Trans. Very Large Scale Integr. Syst.
Circuits Syst. Signal Process.
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Publications
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Raffaele De Rose
,
Marco Lanuzza
,
Fabio Frustaci
,
Sohan Purohit
Designing Dynamic Carry Skip Adders: Analysis and Comparison.
Circuits Syst. Signal Process.
33 (4) (2014)
Sohan Purohit
,
Sai Rahul Chalamalasetti
,
Martin Margala
,
Wim Vanderbauwhede
Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications.
IEEE Trans. Very Large Scale Integr. Syst.
21 (7) (2013)
Sohan Purohit
,
Sai Rahul Chalamalasetti
,
Martin Margala
,
Wim Vanderbauwhede
Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst.
21 (10) (2013)
Sohan Purohit
,
Martin Margala
Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance.
IEEE Trans. Very Large Scale Integr. Syst.
20 (7) (2012)
Wim Vanderbauwhede
,
Sai Rahul Chalamalasetti
,
Sohan Purohit
,
Martin Margala
A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks.
HPCS
(2011)
Sai Rahul Chalamalasetti
,
Sohan Purohit
,
Martin Margala
,
Wim Vanderbauwhede
Radiation-Hardened Reconfigurable Array With Instruction Roll-Back.
IEEE Embed. Syst. Lett.
2 (4) (2010)
Mohamed El-Hadedy
,
Sohan Purohit
,
Martin Margala
,
Svein J. Knapskog
Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems.
AHS
(2010)
Sohan Purohit
,
Sai Rahul Chalamalasetti
,
Martin Margala
Design of self correcting radiation hardened digital circuits using decoupled ground bus.
ACM Great Lakes Symposium on VLSI
(2010)
Sohan Purohit
,
Marco Lanuzza
,
Martin Margala
Design Space Exploration of Split-Path Data Driven Dynamic Full Adder.
J. Low Power Electron.
6 (4) (2010)
Sohan Purohit
,
Sai Rahul Chalamalasetti
,
Martin Margala
Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths.
AHS
(2010)
Wim Vanderbauwhede
,
Martin Margala
,
Sai Rahul Chalamalasetti
,
Sohan Purohit
A C++-embedded Domain-Specific Language for programming the MORA soft processor array.
ASAP
(2010)
Sohan Purohit
,
David Harrington
,
Martin Margala
An area efficient design methodology for SEU tolerant digital circuits.
ISCAS
(2010)
Sai Rahul Chalamalasetti
,
Sohan Purohit
,
Martin Margala
,
Wim Vanderbauwhede
MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor.
AHS
(2009)
Sohan Purohit
,
Marco Lanuzza
,
Stefania Perri
,
Pasquale Corsonello
,
Martin Margala
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath.
VLSI Design
(2009)
Sai Rahul Chalamalasetti
,
Wim Vanderbauwhede
,
Sohan Purohit
,
Martin Margala
A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model.
FPL
(2009)
Wim Vanderbauwhede
,
Martin Margala
,
Sai Rahul Chalamalasetti
,
Sohan Purohit
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor.
ERSA
(2009)
Sohan Purohit
,
Sai Rahul Chalamalasetti
,
Martin Margala
A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic.
ACM Great Lakes Symposium on VLSI
(2009)
Sohan Purohit
,
Marco Lanuzza
,
Stefania Perri
,
Pasquale Corsonello
,
Martin Margala
Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems.
J. Low Power Electron.
5 (3) (2009)
Sohan Purohit
,
Martin Margala
,
Marco Lanuzza
,
Pasquale Corsonello
New performance/power/area efficient, reliable full adder design.
ACM Great Lakes Symposium on VLSI
(2009)
Sohan Purohit
,
Sai Rahul Chalamalasetti
,
Martin Margala
,
Pasquale Corsonello
Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices.
ReConFig
(2008)
Sohan Purohit
,
Sai Rahul Chalamalasetti
,
Martin Margala
,
Pasquale Corsonello
Power/throughput/area efficient PIM-based reconfigurable array for parallel processing.
SoCC
(2008)