Stefania Perri

ORCID

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 43

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. II Express Briefs

Int. J. Circuit Theory Appl.

ICECS

Publications

Stefania Perri
RAW 2024 Invited Talk-2: Digital In-Memory Computing to Accelerate Deep Learning Inference on the Edge. IPDPS (Workshops) (2024)
Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
Approximate bilateral filters for real-time and low-energy imaging applications on FPGAs. J. Supercomput. 80 (11) (2024)
Stefania Perri, Cristian Zambelli, Daniele Ielmini, Cristina Silvano
Digital In-Memory Computing to Accelerate Deep Learning Inference on the Edge. IPDPS (Workshops) (2024)
Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
Efficient implementation of signed multipliers on FPGAs. Comput. Electr. Eng. 116 (2024)
Cosimo Ieracitano, Nadia Mammone, Fanny Spagnolo, Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Francesco Carlo Morabito
An explainable embedded neural system for on-board ship detection from optical satellite imagery. Eng. Appl. Artif. Intell. 133 (2024)
Fanny Spagnolo, Stefania Perri, Massimo Vatalaro, Fabio Frustaci, Felice Crupi, Pasquale Corsonello
Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization. IEEE Trans. Very Large Scale Integr. Syst. 32 (8) (2024)
Fabio Frustaci, Fanny Spagnolo, Stefania Perri, Pasquale Corsonello
A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers. IEEE Trans. Circuits Syst. II Express Briefs 70 (2) (2023)
Fabrizio Ferrandi, Serena Curzel, Leandro Fiorin, Daniele Ielmini, Cristina Silvano, Francesco Conti, Alessio Burrello, Francesco Barchi, Luca Benini, Luciano Lavagno, Teodoro Urso, Enrico Calore, Sebastiano Fabio Schifano, Cristian Zambelli, Maurizio Palesi, Giuseppe Ascia, Enrico Russo, Nicola Petra, Davide De Caro, Gennaro Di Meo, Valeria Cardellini, Salvatore Filippone, Francesco Lo Presti, Francesco Silvestri, Paolo Palazzari, Stefania Perri
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures. CoRR (2023)
Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Stefania Perri, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke
A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. CoRR (2023)
Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
Design of Approximate Bilateral Filters for Image Denoising on FPGAs. IEEE Access 11 (2023)
Cristian Sestito, Stefania Perri, Robert J. Stewart
FPGA Design of Transposed Convolutions for Deep Learning Using High-Level Synthesis. J. Signal Process. Syst. 95 (10) (2023)
Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello
Design of Leading Zero Counters on FPGAs. IEEE Embed. Syst. Lett. 15 (3) (2023)
Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello
Multibit Full Comparator Logic in Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs 69 (11) (2022)
Emanuel Marrazzo, Fanny Spagnolo, Stefania Perri
Runtime Reconfigurable Hardware Accelerator for Energy-Efficient Transposed Convolutions. PRIME (2022)
Fanny Spagnolo, Stefania Perri, Pasquale Corsonello
Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems. IEEE Access 10 (2022)
Fabio Frustaci, Fanny Spagnolo, Stefania Perri, Giuseppe Cocorullo, Pasquale Corsonello
Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes. Sensors 22 (8) (2022)
Cristian Sestito, Stefania Perri, Robert Stewart
Design-Space Exploration of Quantized Transposed Convolutional Neural Networks for FPGA-based Systems-on-Chip. DASC/PiCom/CBDCom/CyberSciTech (2022)
Cristian Sestito, Stefania Perri, Robert Stewart
Accuracy Evaluation of Transposed Convolution-Based Quantized Neural Networks. IJCNN (2022)
Fanny Spagnolo, Stefania Perri, Pasquale Corsonello
Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello
Accuracy Improved Low-Energy Multi-Bit Approximate Adders in QCA. IEEE Trans. Circuits Syst. II Express Briefs 68 (11) (2021)
Cristian Sestito, Fanny Spagnolo, Stefania Perri
Design of Flexible Hardware Accelerators for Image Convolutions and Transposed Convolutions. J. Imaging 7 (10) (2021)
Stefania Perri, Cristian Sestito, Fanny Spagnolo, Pasquale Corsonello
Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip. J. Imaging 6 (9) (2020)
Fanny Spagnolo, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs. ICECS (2020)
Stefania Perri, Fabio Frustaci, Fanny Spagnolo, Pasquale Corsonello
Stereo vision architecture for heterogeneous systems-on-chip. J. Real Time Image Process. 17 (2) (2020)
Cristian Sestito, Fanny Spagnolo, Pasquale Corsonello, Stefania Perri
An Efficient Convolution Engine based on the À-trous Spatial Pyramid Pooling. ASAP (2020)
Fanny Spagnolo, Stefania Perri, Pasquale Corsonello
Design of a real-time face detection architecture for heterogeneous systems-on-chips. Integr. 74 (2020)
Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello
Parallel architecture of power-of-two multipliers for FPGAs. IET Circuits Devices Syst. 14 (3) (2020)
Fanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello
Reconfigurable Convolution Architecture for Heterogeneous Systems-on-Chip. MECO (2020)
Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto
Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation. IEEE Trans. Circuits Syst. (12) (2020)
Fanny Spagnolo, Stefania Perri, Pasquale Corsonello
An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis. Sensors 19 (14) (2019)
Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Lorena-de-los-Angeles Guachi-Guachi, Stefania Perri
Multimodal background subtraction for high-performance embedded systems. J. Real Time Image Process. 16 (5) (2019)
Fanny Spagnolo, Pasquale Corsonello, Stefania Perri
Efficient Architecture for Integral Image Computation on Heterogeneous FPGAs. PRIME (2019)
Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation. IEEE Trans. Very Large Scale Integr. Syst. 27 (4) (2019)
Stefania Perri, Fabio Frustaci, Fanny Spagnolo, Pasquale Corsonello
Design of Real-Time FPGA-based Embedded System for Stereo Vision. ISCAS (2018)
Fanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello
Designing Fast Convolutional Engines for Deep Learning Applications. ICECS (2018)
Fanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems. ICECS (2018)
Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
Design of Efficient BCD Adders in Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs (5) (2017)
Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
Design of efficient QCA multiplexers. Int. J. Circuit Theory Appl. 44 (3) (2016)
Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
An efficient hardware-oriented stereo matching algorithm. Microprocess. Microsystems 46 (2016)
Pasquale Corsonello, Stefania Perri, Fabio Frustaci
Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology. ICCD (2015)
Pasquale Corsonello, Fabio Frustaci, Stefania Perri
Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology. IEEE Trans. Very Large Scale Integr. Syst. 23 (12) (2015)
Pasquale Corsonello, Fabio Frustaci, Stefania Perri
Power supply noise in accurate delay model for the sub-threshold domain. Integr. 50 (2015)
Marco Lanuzza, Pasquale Corsonello, Stefania Perri
Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs. IEEE Trans. Very Large Scale Integr. Syst. 23 (2) (2015)
Lorena Guachi, Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
A novel background subtraction method based on color invariants and grayscale levels. ICCST (2014)
Pasquale Corsonello, Fabio Frustaci, Marco Lanuzza, Stefania Perri
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2014)
Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
Area-Delay Efficient Binary Adders in QCA. IEEE Trans. Very Large Scale Integr. Syst. 22 (5) (2014)
Fabio Frustaci, Marco Lanuzza, Stefania Perri, Pasquale Corsonello
Analyzing noise robustness of wide fan-in dynamic logic gates under process variations. Int. J. Circuit Theory Appl. 42 (5) (2014)
Pasquale Corsonello, Marco Lanuzza, Stefania Perri
Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates. Int. J. Circuit Theory Appl. 42 (1) (2014)
Stefania Perri, Marco Lanuzza, Pasquale Corsonello
Design of high-speed low-power parallel-prefix adder trees in nanometer technologies. Int. J. Circuit Theory Appl. 42 (7) (2014)
Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
Adaptive Census Transform: A novel hardware-oriented stereovision algorithm. Comput. Vis. Image Underst. 117 (1) (2013)
Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
Comparative analysis of yield optimized pulsed flip-flops. Microelectron. Reliab. 52 (8) (2012)
Marco Lanuzza, Pasquale Corsonello, Stefania Perri
Low-Power Level Shifter for Multi-Supply Voltage Designs. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Paolo Zicari, Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
Low-cost FPGA stereo vision system for real time disparity maps calculation. Microprocess. Microsystems 36 (4) (2012)
Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello
Energy-efficient single-clock-cycle binary comparator. Int. J. Circuit Theory Appl. 40 (3) (2012)
Fabio Frustaci, Pasquale Corsonello, Stefania Perri
Analytical Delay Model Considering Variability Effects in Subthreshold Domain. IEEE Trans. Circuits Syst. II Express Briefs (3) (2012)
Stefania Perri, Pasquale Corsonello
Fast-squarer circuits using 3-bit-scan without overlapping bits. Int. J. Circuit Theory Appl. 39 (10) (2011)
Stefania Perri, Pasquale Corsonello
Efficient memory architecture for image processing. Int. J. Circuit Theory Appl. 39 (3) (2011)
Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics. ISVLSI (2010)
Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis. PATMOS (2010)
Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello
A new low-power high-speed single-clock-cycle binary comparator. ISCAS (2010)
Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications. ACM Trans. Reconfigurable Technol. Syst. 4 (1) (2010)
Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. VLSI Design (2009)
Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello
Designing High-Speed Adders in Power-Constrained Environments. IEEE Trans. Circuits Syst. II Express Briefs (2) (2009)
Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello
Low-power split-path data-driven dynamic logic. IET Circuits Devices Syst. 3 (6) (2009)
Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications. ARC (2009)
Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. J. Low Power Electron. 5 (3) (2009)
Stefania Perri, Pasquale Corsonello
Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator. IEEE Trans. Circuits Syst. II Express Briefs (12) (2008)
Paolo Zicari, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
A matrix product accelerator for field programmable systems on chip. Microprocess. Microsystems 32 (2) (2008)
Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
High-performance noise-tolerant circuit techniques for CMOS dynamic logic. IET Circuits Devices Syst. 2 (6) (2008)
Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. PATMOS (2008)
Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation. PATMOS (2008)
Paolo Zicari, Emanuele Sciagura, Stefania Perri, Pasquale Corsonello
A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals. Microprocess. Microsystems 32 (8) (2008)
Emanuele Sciagura, Paolo Zicari, Stefania Perri, Pasquale Corsonello
An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector. DSD (2007)
Stefania Perri, Pasquale Corsonello
VLSI implementations of efficient isotropic flexible 2D convolvers. IET Circuits Devices Syst. 1 (4) (2007)
Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo
Design and Implementation of a 90nm Low bit-rate Image Compression Core. DSD (2007)
Marco Lanuzza, Stefania Perri, Pasquale Corsonello
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing. SAMOS (2007)
Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. AHS (2007)
Paolo Zicari, Pasquale Corsonello, Stefania Perri
An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs. ICECS (2006)
Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo
Low bit rate image compression core for onboard space applications. IEEE Trans. Circuits Syst. Video Technol. 16 (1) (2006)
Stefania Perri, Maria Antonia Iachino, Pasquale Corsonello
Simd Multipliers for Accelerating Embedded Processors in FPGAS. J. Circuits Syst. Comput. 15 (4) (2006)
Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
Leakage energy reduction techniques in deep submicron cache memories: a comparative study. ISCAS (2006)
Pasquale Corsonello, Stefania Perri, Martin Margala
An integrated countermeasure against differential power analysis for secure smart-cards. ISCAS (2006)
Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories. IEEE Trans. Very Large Scale Integr. Syst. 14 (11) (2006)
Stefania Perri, Daniela Colonna, Paolo Zicari, Pasquale Corsonello
SAD-Based Stereo Matching Circuit for FPGAs. ICECS (2006)
Pasquale Corsonello, Stefania Perri, Martin Margala
Efficient Addition Circuits for Modular Design of Processors-in-Memory. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2005)
Marco Lanuzza, Stefania Perri, Martin Margala, Pasquale Corsonello
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. FPL (2005)
Pasquale Corsonello, Stefania Perri
Efficient Reconfigurable Manchester Adders for Low-power Media Processing. J. Circuits Syst. Comput. 14 (1) (2005)
Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
Fast Low-Power 64-Bit Modular Hybrid Adder. PATMOS (2005)
Pasquale Corsonello, Stefania Perri, Paolo Zicari, Giuseppe Cocorullo
Microprocessor-based FPGA implementation of SPIHT image compression subsystems. Microprocess. Microsystems 29 (6) (2005)
Stefania Perri, Marco Lanuzza, Pasquale Corsonello, Giuseppe Cocorullo
A high-performance fully reconfigurable FPGA-based 2D convolution processor. Microprocess. Microsystems 29 (8-9) (2005)
Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, Marco Lanuzza, Giuseppe Cocorullo
Variable precision arithmetic circuits for FPGA-based multimedia processors. IEEE Trans. Very Large Scale Integr. Syst. 12 (9) (2004)
Pasquale Corsonello, Stefania Perri, Vitit Kantabutra
Area- and Power-Reduced Standard-Cell Spanning Tree Adders. ESA/VLSI (2004)
Stefania Perri, Pasquale Corsonello, Giovanni Staino
A low-power sub-nanosecond standard-cells based adder. ICECS (2003)
Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
A high-speed energy-efficient 64-bit reconfigurable binary adder. IEEE Trans. Very Large Scale Integr. Syst. 11 (5) (2003)
Pasquale Corsonello, Stefania Perri, Maria Antonia Iachino, Giuseppe Cocorullo
Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems. FPL (2003)
Stefania Perri, Maria Antonia Iachino, Pasquale Corsonello
Speed-efficient wide adders for VIRTEX FPGAs. ICECS (2002)
Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
VLSI circuits for low-power high-speed asynchronous addition. IEEE Trans. Very Large Scale Integr. Syst. 10 (5) (2002)
Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo, Stefania Perri, Giovanni Staino
Dynamic power of CMOS gates driving lossy transmission lines. ICECS (2001)
Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, Gregorio Cappuccino, Giovanni Staino
VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits. ICECS (2001)
Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. PATMOS (2000)

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Publication Activity (10 Years)

Top Topics

Top Venues

Stefania Perri