Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates.

Pasquale Corsonello Marco Lanuzza Stefania Perri

Published in: Int. J. Circuit Theory Appl. (2014)

Keyphrases

high speed
low power
logic circuits
delay insensitive
real time
power consumption
lower level
cmos technology
low cost
human body
frame rate
predicate logic
nm technology
asynchronous circuits
classical logic
image sensor
levels of abstraction
modal logic
higher level
data sets