Marco Lanuzza

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 59

Top Topics

Approximate Matching

Hamming Distance

Content Addressable Memory

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Int. J. Circuit Theory Appl.

Publications

Esteban Garzón, Robert Hanhan, Marco Lanuzza, Adam Teman, Leonid Yavits
FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture. IEEE Access 12 (2024)
Hanan Marinberg, Esteban Garzón, Tzachi Noy, Marco Lanuzza, Adam Teman
Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach. IEEE Access 11 (2023)
Ariana Musello, Esteban Garzón, Marco Lanuzza, Luis-Miguel Prócel, Ramiro Taco
XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs. IEEE Trans. Circuits Syst. II Express Briefs 70 (3) (2023)
Esteban Garzón, Leonid Yavits, Adam Teman, Marco Lanuzza
STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications. LASCAS (2023)
Esteban Garzón, Leonid Yavits, Giovanni Finocchio, Mario Carpentieri, Adam Teman, Marco Lanuzza
A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation. IEEE Access 11 (2023)
Esteban Garzón, Roman Golman, Marco Lanuzza, Adam Teman, Leonid Yavits
A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory. IEEE Trans. Circuits Syst. II Express Briefs 70 (10) (2023)
Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V. IEEE Access 11 (2023)
Tatiana Moposita, Esteban Garzón, Felice Crupi, Lionel Trojman, Andrei Vladimirescu, Marco Lanuzza
Efficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing. IEEE Trans. Circuits Syst. II Express Briefs 70 (3) (2023)
Esteban Garzón, Marco Lanuzza, Adam Teman, Leonid Yavits
: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (1) (2023)
Tatiana Moposita, Esteban Garzón, Raffaele De Rose, Felice Crupi, Andrei Vladimirescu, Lionel Trojman, Marco Lanuzza
SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing. IEEE Access 11 (2023)
Tatiana Moposita, Lionel Trojman, Felice Crupi, Marco Lanuzza, Andrei Vladimirescu
Voltage-to-Voltage Sigmoid Neuron Activation Function Design for Artificial Neural Networks. LASCAS (2022)
Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification. IEEE Access 10 (2022)
Massimo Vatalaro, Raffaele De Rose, Marco Lanuzza, Felice Crupi
Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider. ICECS 2022 (2022)
Benjamin Zambrano, Esteban Garzón, Sebastiano Strangio, Giuseppe Iannaccone, Marco Lanuzza
A 0.6V$-$1.8V Compact Temperature Sensor with 0.24°C Resolution, $\pm$1.4°C Inaccuracy and 1.06nJ per Conversion. CoRR (2022)
Esteban Garzón, Adam Teman, Marco Lanuzza, Leonid Yavits
AIDA: Associative In-Memory Deep Learning Accelerator. IEEE Micro 42 (6) (2022)
Raffaele De Rose, Tommaso Zanotti, Francesco Maria Puglisi, Felice Crupi, Paolo Pavan, Marco Lanuzza
Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing. CoRR (2022)
Esteban Garzón, Ramiro Taco, Luis-Miguel Prócel, Lionel Trojman, Marco Lanuzza
Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories. LASCAS (2022)
Esteban Garzón, Roman Golman, Odem Harel, Tzachi Noy, Yehuda Kra, Asaf Pollock, Slava Yuzhaninov, Yonatan Shoshan, Yehuda Rudin, Yoav Weizman, Marco Lanuzza, Adam Teman
A RISC-V-based Research Platform for Rapid Design Cycle. ISCAS (2022)
Benjamin Zambrano, Esteban Garzón, Sebastiano Strangio, Felice Crupi, Marco Lanuzza
A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Massimo Vatalaro, Raffaele De Rose, Marco Lanuzza, Felice Crupi
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm. IEEE J. Solid State Circuits 57 (8) (2022)
Robert Hanhan, Esteban Garzón, Zuher Jahshan, Adam Teman, Marco Lanuzza, Leonid Yavits
EDAM: edit distance tolerant approximate matching content addressable memory. ISCA (2022)
Benjamin Zambrano, Sebastiano Strangio, Tommaso Rizzo, Esteban Garzón, Marco Lanuzza, Giuseppe Iannaccone
All-Analog Silicon Integration of Image Sensor and Neural Computing Engine for Image Classification. IEEE Access 10 (2022)
Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Adam Teman, Marco Lanuzza
Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs. CoRR (2022)
Luigi Fassio, Francesco Settino, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter. IEEE Trans. Circuits Syst. II Express Briefs 68 (4) (2021)
Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
A 0.6-to-1.8V CMOS Current Reference With Near-100% Power Utilization. IEEE Trans. Circuits Syst. II Express Briefs 68 (9) (2021)
Carmelo Felicetti, Marco Lanuzza, Antonino Rullo, Domenico Saccà, Felice Crupi
Exploiting Silicon Fingerprint for Device Authentication Using CMOS-PUF and ECC. SmartIoT (2021)
Esteban Garzón, Yosi Greenblatt, Odem Harel, Marco Lanuzza, Adam Teman
Gain-Cell Embedded DRAM Under Cryogenic Operation - A First Study. IEEE Trans. Very Large Scale Integr. Syst. 29 (7) (2021)
Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy. ESSCIRC (2021)
Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for Approximate Matching Applications. CoRR (2021)
Ricardo Escobar, Luis-Miguel Prócel, Lionel Trojman, Marco Lanuzza, Ramiro Taco
High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. LASCAS (2021)
Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish
Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. ISCAS (2021)
Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW. IEEE J. Solid State Circuits 56 (10) (2021)
Lionel Trojman, David Rivadeneira, Marco Villegas, Eliana Acurio, Marco Lanuzza, Luis-Miguel Procel, Ramiro Taco
RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies. LASCAS (2021)
Netanel Shavit, Inbal Stanger, Ramiro Taco, Marco Lanuzza, Alexander Fish
Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET. ISCAS (2021)
Inbal Stanger, Netanel Shavit, Ramiro Taco, Leonid Yavits, Marco Lanuzza, Alexander Fish
Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance. ISCAS (2020)
Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
Area in 180nm. VLSI Circuits (2020)
Ramiro Taco, Leonid Yavits, Netanel Shavit, Inbal Stanger, Marco Lanuzza, Alexander Fish
Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology. ISCAS (2020)
Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish
Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. IEEE Trans. Circuits Syst. II Express Briefs (9) (2020)
Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Giovanni Finocchio, Mario Carpentieri, Marco Lanuzza
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework. Integr. 71 (2020)
Marco Lanuzza, Raffaele De Rose, Esteban Garzón, Felice Crupi
Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers. ASICON (2019)
Marco Lanuzza, Raffaele De Rose, Felice Crupi, Massimo Alioto
An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops. ICECS (2019)
Carmelo Felicetti, Angelo Furfaro, Domenico Saccà, Massimo Vatalaro, Marco Lanuzza, Felice Crupi
Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions. IDCS (2019)
Esteban Garzón, Raffaele De Rose, Felice Crupi, Marco Lanuzza
Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory. ICECS (2019)
Raffaele De Rose, Paul Romero, Marco Lanuzza
Double-precision Dual Mode Logic carry-save multiplier. Integr. 64 (2019)
Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI. IEEE J. Solid State Circuits 54 (2) (2019)
Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish
Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI. ISCAS (2019)
Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Giovanni Finocchio, Mario Carpentieri, Marco Lanuzza
Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. SMACD (2019)
Raffaele De Rose, Felice Crupi, Maksym Paliy, Marco Lanuzza, Giuseppe Iannaccone
Design of a 3T current reference for low-voltage, low-power operation. ICICDT (2018)
Noemi Guerra, Raffaele De Rose, Marco Guevara, Paul Procel, Marco Lanuzza, Felice Crupi
Impact of the Emitter Contact Pattern in c-Si BC- BJ Solar Cells by Numerical Simulations. RTSI (2018)
Raffaele De Rose, Marco Lanuzza, Felice Crupi, Giulio Siracusano, Riccardo Tomasello, Giovanni Finocchio, Mario Carpentieri, Massimo Alioto
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2018)
Felice Crupi, Raffaele De Rose, Maksym Paliy, Marco Lanuzza, Mattia Perna, Giuseppe Iannaccone
A portable class of 3-transistor current references with low-power sub-0.5 V operation. Int. J. Circuit Theory Appl. 46 (4) (2018)
Raffaele De Rose, Greta Carangelo, Marco Lanuzza, Felice Crupi, Giovanni Finocchio, Mario Carpentieri
Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework. SMACD (2017)
Marco Lanuzza, Felice Crupi, Sandro Rao, Raffaele De Rose, Giuseppe Iannaccone
Low energy/delay overhead level shifter for wide-range voltage conversion. Int. J. Circuit Theory Appl. 45 (11) (2017)
Marco Lanuzza, Felice Crupi, Sandro Rao, Raffaele De Rose, Sebastiano Strangio, Giuseppe Iannaccone
An Ultralow-Voltage Energy-Efficient Level Shifter. IEEE Trans. Circuits Syst. II Express Briefs (1) (2017)
Raffaele De Rose, Felice Crupi, Marco Lanuzza, Domenico Albano
A physical unclonable function based on a 2-transistor subthreshold voltage divider. Int. J. Circuit Theory Appl. 45 (2) (2017)
Raffaele De Rose, Marco Lanuzza, Felice Crupi, Giulio Siracusano, Riccardo Tomasello, Giovanni Finocchio, Mario Carpentieri, Massimo Alioto
A variation-aware simulation framework for hybrid CMOS/spintronic circuits. ISCAS (2017)
Raffaele De Rose, Domenico Albano, Felice Crupi, Marco Lanuzza
Design of a sub-1-V nanopower CMOS current reference. ECCTD (2017)
Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish
Evaluation of Dual Mode Logic in 28nm FD-SOI technology. ISCAS (2017)
Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish
Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology. ISCAS (2016)
Ramiro Taco, Marco Lanuzza, Domenico Albano
Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits. VLSI Design 2015 (2015)
Domenico Albano, Marco Lanuzza, Ramiro Taco, Felice Crupi
Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines. Int. J. Circuit Theory Appl. 43 (11) (2015)
Marco Lanuzza, Pasquale Corsonello, Stefania Perri
Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs. IEEE Trans. Very Large Scale Integr. Syst. 23 (2) (2015)
Pasquale Corsonello, Fabio Frustaci, Marco Lanuzza, Stefania Perri
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2014)
Fabio Frustaci, Marco Lanuzza, Stefania Perri, Pasquale Corsonello
Analyzing noise robustness of wide fan-in dynamic logic gates under process variations. Int. J. Circuit Theory Appl. 42 (5) (2014)
Pasquale Corsonello, Marco Lanuzza, Stefania Perri
Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates. Int. J. Circuit Theory Appl. 42 (1) (2014)
Marco Lanuzza, Ramiro Taco, Domenico Albano
Dynamic gate-level body biasing for subthreshold digital design. LASCAS (2014)
Raffaele De Rose, Marco Lanuzza, Fabio Frustaci, Sohan Purohit
Designing Dynamic Carry Skip Adders: Analysis and Comparison. Circuits Syst. Signal Process. 33 (4) (2014)
Stefania Perri, Marco Lanuzza, Pasquale Corsonello
Design of high-speed low-power parallel-prefix adder trees in nanometer technologies. Int. J. Circuit Theory Appl. 42 (7) (2014)
Marco Lanuzza, Ramiro Taco
Improving speed and power characteristics of pulse-triggered flip-flops. LASCAS (2014)
Marco Lanuzza
A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops. J. Low Power Electron. 9 (4) (2013)
Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
Comparative analysis of yield optimized pulsed flip-flops. Microelectron. Reliab. 52 (8) (2012)
Marco Lanuzza, Pasquale Corsonello, Stefania Perri
Low-Power Level Shifter for Multi-Supply Voltage Designs. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello
Energy-efficient single-clock-cycle binary comparator. Int. J. Circuit Theory Appl. 40 (3) (2012)
Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics. ISVLSI (2010)
Sumit Kansal, Marco Lanuzza, Pasquale Corsonello
Impact of Random Process Variations on Different 65nm SRAM Cell Topologies. ICETET (2010)
Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis. PATMOS (2010)
Sohan Purohit, Marco Lanuzza, Martin Margala
Design Space Exploration of Split-Path Data Driven Dynamic Full Adder. J. Low Power Electron. 6 (4) (2010)
Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello
A new low-power high-speed single-clock-cycle binary comparator. ISCAS (2010)
Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications. ACM Trans. Reconfigurable Technol. Syst. 4 (1) (2010)
Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. VLSI Design (2009)
Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello
Designing High-Speed Adders in Power-Constrained Environments. IEEE Trans. Circuits Syst. II Express Briefs (2) (2009)
Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello
Low-power split-path data-driven dynamic logic. IET Circuits Devices Syst. 3 (6) (2009)
Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications. ARC (2009)
Fabio Frustaci, Marco Lanuzza
A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder. PATMOS (2009)
Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. J. Low Power Electron. 5 (3) (2009)
Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello
New performance/power/area efficient, reliable full adder design. ACM Great Lakes Symposium on VLSI (2009)
Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. PATMOS (2008)
Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo
Design and Implementation of a 90nm Low bit-rate Image Compression Core. DSD (2007)
Marco Lanuzza, Stefania Perri, Pasquale Corsonello
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing. SAMOS (2007)
Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. AHS (2007)
Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo
Low bit rate image compression core for onboard space applications. IEEE Trans. Circuits Syst. Video Technol. 16 (1) (2006)
Marco Lanuzza, Stefania Perri, Martin Margala, Pasquale Corsonello
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. FPL (2005)
Marco Lanuzza, Martin Margala, Pasquale Corsonello
Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. ISLPED (2005)
Stefania Perri, Marco Lanuzza, Pasquale Corsonello, Giuseppe Cocorullo
A high-performance fully reconfigurable FPGA-based 2D convolution processor. Microprocess. Microsystems 29 (8-9) (2005)
Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, Marco Lanuzza, Giuseppe Cocorullo
Variable precision arithmetic circuits for FPGA-based multimedia processors. IEEE Trans. Very Large Scale Integr. Syst. 12 (9) (2004)