Ramiro Taco

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 21

Top Topics

Energy Efficiency

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE J. Solid State Circuits

Publications

Netanel Shavit, Inbal Stanger, Ramiro Taco, Leonid Yavits, Alexander Fish
Low Power, Energy Efficient and High Performance Triple Mode Logic for IoT Applications. PRIME (2024)
Ariana Musello, Esteban Garzón, Marco Lanuzza, Luis-Miguel Prócel, Ramiro Taco
XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs. IEEE Trans. Circuits Syst. II Express Briefs 70 (3) (2023)
Santiago S. Pérez, Alessandro Bedoya, Luis-Miguel Prócel, Ramiro Taco
Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages. LASCAS (2023)
Netanel Shavit, Inbal Stanger, Ramiro Taco, Alexander Fish, Itamar Levi
Programmable All-in-One 4×8-/2×16-/1×32-Bits Dual Mode Logic Multiplier in 16 nm FinFET With Semi-Automatic Flow. IEEE Access 11 (2023)
Esteban Garzón, Ramiro Taco, Luis-Miguel Prócel, Lionel Trojman, Marco Lanuzza
Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories. LASCAS (2022)
Yizhak Shifman, Inbal Stanger, Netanel Shavit, Ramiro Taco, Alexander Fish, Joseph Shor
A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic. IEEE J. Solid State Circuits 57 (2) (2022)
Kevin Vicuña, Luis-Miguel Prócel, Lionel Trojman, Ramiro Taco
DMTJ-Based Non-Volatile Ternary Content Addressable Memory for Energy-Efficient High-Performance Systems. LASCAS (2022)
Ariana Musello, Santiago S. Pérez, Marco Villegas, Luis-Miguel Prócel, Ramiro Taco, Lionel Trojman
Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells. LASCAS (2022)
Ricardo Escobar, Luis-Miguel Prócel, Lionel Trojman, Marco Lanuzza, Ramiro Taco
High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. LASCAS (2021)
Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish
Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. ISCAS (2021)
Lionel Trojman, David Rivadeneira, Marco Villegas, Eliana Acurio, Marco Lanuzza, Luis-Miguel Procel, Ramiro Taco
RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies. LASCAS (2021)
Netanel Shavit, Inbal Stanger, Ramiro Taco, Marco Lanuzza, Alexander Fish
Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET. ISCAS (2021)
Inbal Stanger, Netanel Shavit, Ramiro Taco, Leonid Yavits, Marco Lanuzza, Alexander Fish
Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance. ISCAS (2020)
Esteban Garzón, Benjamin Zambrano, Tatiana Moposita, Ramiro Taco, Luis-Miguel Prócel, Lionel Trojman
Reconfigurable CMOS/STT-MTJ Non-Volatile Circuit for Logic-in-Memory Applications. LASCAS (2020)
Ramiro Taco, Leonid Yavits, Netanel Shavit, Inbal Stanger, Marco Lanuzza, Alexander Fish
Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology. ISCAS (2020)
Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish
Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. IEEE Trans. Circuits Syst. II Express Briefs (9) (2020)
Leonid Yavits, Ramiro Taco, Netanel Shavit, Inbal Stanger, Alexander Fish
Dual Mode Logic Address Decoder. ISCAS (2020)
Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI. IEEE J. Solid State Circuits 54 (2) (2019)
Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish
Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI. ISCAS (2019)
Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish
Evaluation of Dual Mode Logic in 28nm FD-SOI technology. ISCAS (2017)
Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish
Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology. ISCAS (2016)
Ramiro Taco, Marco Lanuzza, Domenico Albano
Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits. VLSI Design 2015 (2015)
Domenico Albano, Marco Lanuzza, Ramiro Taco, Felice Crupi
Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines. Int. J. Circuit Theory Appl. 43 (11) (2015)
Marco Lanuzza, Ramiro Taco, Domenico Albano
Dynamic gate-level body biasing for subthreshold digital design. LASCAS (2014)
Marco Lanuzza, Ramiro Taco
Improving speed and power characteristics of pulse-triggered flip-flops. LASCAS (2014)