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An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI.
Ramiro Taco
Itamar Levi
Marco Lanuzza
Alexander Fish
Published in:
IEEE J. Solid State Circuits (2019)
Keyphrases
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high speed
clock gating
power consumption
silicon on insulator
nm technology
flip flops
random access memory
cmos technology
hough transform
logical operations
power dissipation
logic programming
multi valued
primal dual
interior point methods
clock frequency
hardware implementation
low power