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A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits.

Raffaele De RoseMarco LanuzzaFelice CrupiGiulio SiracusanoRiccardo TomaselloGiovanni FinocchioMario CarpentieriMassimo Alioto
Published in: IEEE Trans. Circuits Syst. I Regul. Pap. (2018)
Keyphrases
  • high speed
  • circuit design
  • analog vlsi
  • delay insensitive
  • asynchronous circuits
  • vlsi circuits
  • data sets
  • hybrid learning
  • neural network
  • power consumption
  • modeling language
  • floating gate