Tommaso Zanotti

Publication Activity (10 Years)

Years Active: 2019-2022
Publications (10 Years): 8

Top Topics

Memory Hierarchy

Delay Insensitive

Logic Synthesis

Top Venues

IEEE J. Emerg. Sel. Topics Circuits Syst.

Publications

Raffaele De Rose, Tommaso Zanotti, Francesco Maria Puglisi, Felice Crupi, Paolo Pavan, Marco Lanuzza
Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing. CoRR (2022)
Tommaso Zanotti, Paolo Pavan, Francesco Maria Puglisi
Self-consistent Automated Parameter Extraction of RRAM Physics-Based Compact Model. ESSDERC (2022)
Francesco Maria Puglisi, Tommaso Zanotti, Paolo Pavan
Optimized Synthesis Method for Ultra-Low Power Multi-Input Material Implication Logic With Emerging Non-Volatile Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (11) (2021)
Tommaso Zanotti, Francesco Maria Puglisi, Paolo Pavan
Low-Bit Precision Neural Network Architecture with High Immunity to Variability and Random Telegraph Noise based on Resistive Memories. IRPS (2021)
Tommaso Zanotti, Francesco Maria Puglisi, Paolo Pavan
Smart Logic-in-Memory Architecture For Ultra-Low Power Large Fan-In Operations. AICAS (2020)
Tommaso Zanotti, Francesco Maria Puglisi, Paolo Pavan
Reconfigurable Smart In-Memory Computing Platform Supporting Logic and Binarized Neural Networks for Low-Power Edge Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 10 (4) (2020)
Tommaso Zanotti, Francesco Maria Puglisi, Paolo Pavan
Circuit Reliability Analysis of RRAM-based Logic-in-Memory Crossbar Architectures Including Line Parasitic Effects, Variability, and Random Telegraph Noise. IRPS (2020)
Francesco Maria Puglisi, Tommaso Zanotti, Paolo Pavan
SIMPLY: Design of a RRAM-Based Smart Logic-in-Memory Architecture using RRAM Compact Model. ESSDERC (2019)