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Circuit Reliability Analysis of RRAM-based Logic-in-Memory Crossbar Architectures Including Line Parasitic Effects, Variability, and Random Telegraph Noise.
Tommaso Zanotti
Francesco Maria Puglisi
Paolo Pavan
Published in:
IRPS (2020)
Keyphrases
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reliability analysis
logic synthesis
digital circuits
logic circuits
delay insensitive
chip design
memory hierarchy
power dissipation
shift register
microstrip
genetic algorithm
memory management
circuit design
input output
multi objective
control system
decision trees