Design of high-speed low-power parallel-prefix adder trees in nanometer technologies.
Stefania PerriMarco LanuzzaPasquale CorsonelloPublished in: Int. J. Circuit Theory Appl. (2014)
Keyphrases
- low power
- high speed
- logic circuits
- single chip
- power dissipation
- low cost
- low power consumption
- power consumption
- vlsi architecture
- digital signal processing
- gate array
- cmos technology
- mixed signal
- wireless transmission
- power reduction
- ultra low power
- high power
- analog to digital converter
- design process
- tree structure
- design considerations
- massively parallel
- bit parallel
- shared memory
- data flow