Giuseppe Cocorullo

Publication Activity (10 Years)

Years Active: 1998-2022
Publications (10 Years): 7

Top Topics

Background Subtraction

Foreground Segmentation

Cellular Automata

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Int. J. Circuit Theory Appl.

Microprocess. Microsystems

Publications

Fabio Frustaci, Fanny Spagnolo, Stefania Perri, Giuseppe Cocorullo, Pasquale Corsonello
Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes. Sensors 22 (8) (2022)
Sandro Rao, Elisa Demetra Mallemace, Giuseppe Cocorullo, Lakhdar Dehimi, Francesco Giuseppe Della Corte
Junction Temperature Measurement in Optically-Controlled Power Mosfet. PHOTOPTICS (2021)
Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Lorena-de-los-Angeles Guachi-Guachi, Stefania Perri
Multimodal background subtraction for high-performance embedded systems. J. Real Time Image Process. 16 (5) (2019)
Antonio Cordopatri, Giuseppe Cocorullo
A Smart Torque Control for a High Efficiency 4WD Electric Vehicle. ApplePies (2018)
Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
Design of Efficient BCD Adders in Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs (5) (2017)
Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
Design of efficient QCA multiplexers. Int. J. Circuit Theory Appl. 44 (3) (2016)
Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
An efficient hardware-oriented stereo matching algorithm. Microprocess. Microsystems 46 (2016)
Lorena Guachi, Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
A novel background subtraction method based on color invariants and grayscale levels. ICCST (2014)
Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
Area-Delay Efficient Binary Adders in QCA. IEEE Trans. Very Large Scale Integr. Syst. 22 (5) (2014)
Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
Adaptive Census Transform: A novel hardware-oriented stereovision algorithm. Comput. Vis. Image Underst. 117 (1) (2013)
Paolo Zicari, Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
Low-cost FPGA stereo vision system for real time disparity maps calculation. Microprocess. Microsystems 36 (4) (2012)
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
Design approach for high-bandwidth low-power three-stage operational amplifiers. Int. J. Circuit Theory Appl. 40 (3) (2012)
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
Corrections to "Settling Time Optimization for Three-Stage CMOS Amplifier Topologies" [Dec 09 2569-2582]. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2010)
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2010)
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
Analysis of op-amp phase margin impact on SC SigmaDelta modulator performance. Microelectron. J. 41 (7) (2010)
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
Settling Time Optimization for Three-Stage CMOS Amplifier Topologies. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2009)
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
Effect of OP-amp Phase Margin on SC SigmaDelta Modulator Performances. ISCAS (2009)
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs (1) (2008)
Paolo Zicari, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
A matrix product accelerator for field programmable systems on chip. Microprocess. Microsystems 32 (2) (2008)
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers. PATMOS (2008)
Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
High-performance noise-tolerant circuit techniques for CMOS dynamic logic. IET Circuits Devices Syst. 2 (6) (2008)
Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation. PATMOS (2008)
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
Settling Time Minimization of Operational Amplifiers. PATMOS (2007)
Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo
Design and Implementation of a 90nm Low bit-rate Image Compression Core. DSD (2007)
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
Design methodology of nested-Miller amplifiers for small capacitive loads. ECCTD (2007)
Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo
Low bit rate image compression core for onboard space applications. IEEE Trans. Circuits Syst. Video Technol. 16 (1) (2006)
Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
Leakage energy reduction techniques in deep submicron cache memories: a comparative study. ISCAS (2006)
Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories. IEEE Trans. Very Large Scale Integr. Syst. 14 (11) (2006)
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique. PATMOS (2006)
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications. PATMOS (2006)
Gregorio Cappuccino, Andrea Pugliese, Giuseppe Cocorullo
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation. PATMOS (2005)
Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
Fast Low-Power 64-Bit Modular Hybrid Adder. PATMOS (2005)
Pasquale Corsonello, Stefania Perri, Paolo Zicari, Giuseppe Cocorullo
Microprocessor-based FPGA implementation of SPIHT image compression subsystems. Microprocess. Microsystems 29 (6) (2005)
Stefania Perri, Marco Lanuzza, Pasquale Corsonello, Giuseppe Cocorullo
A high-performance fully reconfigurable FPGA-based 2D convolution processor. Microprocess. Microsystems 29 (8-9) (2005)
Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, Marco Lanuzza, Giuseppe Cocorullo
Variable precision arithmetic circuits for FPGA-based multimedia processors. IEEE Trans. Very Large Scale Integr. Syst. 12 (9) (2004)
Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
A high-speed energy-efficient 64-bit reconfigurable binary adder. IEEE Trans. Very Large Scale Integr. Syst. 11 (5) (2003)
Pasquale Corsonello, Stefania Perri, Maria Antonia Iachino, Giuseppe Cocorullo
Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems. FPL (2003)
Gregorio Cappuccino, Giuseppe Cocorullo
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines. PATMOS (2002)
Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
VLSI circuits for low-power high-speed asynchronous addition. IEEE Trans. Very Large Scale Integr. Syst. 10 (5) (2002)
Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo, Stefania Perri, Giovanni Staino
Dynamic power of CMOS gates driving lossy transmission lines. ICECS (2001)
Gregorio Cappuccino, Giuseppe Cocorullo
CMOS sizing rule for high performance long interconnects. DATE (2001)
Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, Gregorio Cappuccino, Giovanni Staino
VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits. ICECS (2001)
Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. PATMOS (2000)
Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
Designing High-Speed Asynchronous Pipelines. EUROMICRO (2000)
Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
A 56-bit self-timed adder for high speed asynchronous datapath. ICECS (1999)
Gregorio Cappuccino, Giuseppe Cocorullo
A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines. EUROMICRO (1999)
Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo
High performance VLSI modules for division and square root. Microprocess. Microsystems 22 (5) (1998)