VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits.
Stefania PerriPasquale CorsonelloGiuseppe CocorulloGregorio CappuccinoGiovanni StainoPublished in: ICECS (2001)
Keyphrases
- low power
- vlsi implementation
- vlsi architecture
- logic circuits
- power dissipation
- power consumption
- high speed
- random access memory
- cmos technology
- low cost
- flip flops
- delay insensitive
- shift register
- vlsi circuits
- mixed signal
- analog vlsi
- analog to digital converter
- chip design
- data flow
- circuit design
- image sensor
- digital signal processing
- low voltage
- fir filters
- multiscale
- filter bank
- pattern recognition