Andrea Pugliese

Publication Activity (10 Years)

Years Active: 2005-2012
Publications (10 Years): 0

Top Topics

Cmos Technology

Digital Signal Processing

Low Power Consumption

Top Venues

Int. J. Circuit Theory Appl.

Publications

Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
Design approach for high-bandwidth low-power three-stage operational amplifiers. Int. J. Circuit Theory Appl. 40 (3) (2012)
Francesco A. Amoroso, Andrea Pugliese, Gregorio Cappuccino
A new efficient SC integrator scheme for high-speed low-power applications. Int. J. Circuit Theory Appl. 40 (8) (2012)
Francesco A. Amoroso, Andrea Pugliese, Gregorio Cappuccino
Design criterion for high-speed low-power SC circuits. Int. J. Circuit Theory Appl. 39 (10) (2011)
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
Corrections to "Settling Time Optimization for Three-Stage CMOS Amplifier Topologies" [Dec 09 2569-2582]. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2010)
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2010)
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
Analysis of op-amp phase margin impact on SC SigmaDelta modulator performance. Microelectron. J. 41 (7) (2010)
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
Settling Time Optimization for Three-Stage CMOS Amplifier Topologies. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2009)
Gregorio Cappuccino, Francesco A. Amoroso, Andrea Pugliese
Class-AB output stage design for high-speed three-stage op-amps. ICECS (2009)
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
Effect of OP-amp Phase Margin on SC SigmaDelta Modulator Performances. ISCAS (2009)
Francesco A. Amoroso, Andrea Pugliese, Gregorio Cappuccino
Design considerations for fast-settling two-stage Miller-compensated operational amplifiers. ICECS (2009)
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs (1) (2008)
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo
Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers. PATMOS (2008)
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
Settling Time Minimization of Operational Amplifiers. PATMOS (2007)
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
Design methodology of nested-Miller amplifiers for small capacitive loads. ECCTD (2007)
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique. PATMOS (2006)
Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications. PATMOS (2006)
Gregorio Cappuccino, Andrea Pugliese, Giuseppe Cocorullo
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation. PATMOS (2005)