Design criterion for high-speed low-power SC circuits.
Francesco A. AmorosoAndrea PuglieseGregorio CappuccinoPublished in: Int. J. Circuit Theory Appl. (2011)
Keyphrases
- low power
- high speed
- logic circuits
- single chip
- power dissipation
- cmos technology
- low power consumption
- vlsi architecture
- mixed signal
- power consumption
- power reduction
- low cost
- high power
- digital signal processing
- gate array
- wireless transmission
- vlsi circuits
- nm technology
- ultra low power
- real time
- delay insensitive
- image sensor
- vlsi implementation
- efficient implementation
- design process
- shift register