VLSI Implementation of a Low-Power High-Speed Self-Timed Adder.

Pasquale Corsonello Stefania Perri Giuseppe Cocorullo

Published in: PATMOS (2000)

Keyphrases

low power
high speed
vlsi implementation
vlsi architecture
logic circuits
power dissipation
power consumption
digital signal processing
gate array
low cost
low power consumption
power reduction
data flow
fir filters
associative memory
frame rate
filter bank
cmos technology
image processing
mixed signal
neural network