A 56-bit self-timed adder for high speed asynchronous datapath.
Pasquale CorsonelloStefania PerriGiuseppe CocorulloPublished in: ICECS (1999)
Keyphrases
- high speed
- shift register
- low power
- logic circuits
- power dissipation
- delay insensitive
- bit parallel
- high speed networks
- digital signal processing
- data flow
- low latency
- random number generator
- frame rate
- real time
- power consumption
- bit rate
- signature file
- case study
- decision trees
- genetic algorithm
- machine learning
- data mining