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A low-power sub-nanosecond standard-cells based adder.
Stefania Perri
Pasquale Corsonello
Giovanni Staino
Published in:
ICECS (2003)
Keyphrases
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low power
logic circuits
low cost
power consumption
high speed
power dissipation
single chip
wireless transmission
digital signal processing
vlsi circuits
high power
vlsi architecture
power reduction
low power consumption
delay insensitive
gate array
ultra low power
cmos technology
high definition television