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An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector.
Emanuele Sciagura
Paolo Zicari
Stefania Perri
Pasquale Corsonello
Published in:
DSD (2007)
Keyphrases
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hardware implementation
real time
asynchronous circuits
error rate
hardware architecture
relevance feedback
high speed
management system
hardware architectures
software implementation
hardware design
network architecture
design principles
data acquisition
detection method
dedicated hardware
low cost