Giuseppe Ascia

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 23

Top Topics

Design Space Exploration

Routing Algorithm

Top Venues

Publications

Enrico Russo, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Salvatore Monteleone, Vincenzo Catania
Memory-Aware DNN Algorithm-Hardware Mapping via Integer Linear Programming. CF (2023)
Enrico Russo, Maurizio Palesi, Davide Patti, Salvatore Monteleone, Giuseppe Ascia, Vincenzo Catania
Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators. IEEE Internet Things J. 10 (2) (2023)
Fabrizio Ferrandi, Serena Curzel, Leandro Fiorin, Daniele Ielmini, Cristina Silvano, Francesco Conti, Alessio Burrello, Francesco Barchi, Luca Benini, Luciano Lavagno, Teodoro Urso, Enrico Calore, Sebastiano Fabio Schifano, Cristian Zambelli, Maurizio Palesi, Giuseppe Ascia, Enrico Russo, Nicola Petra, Davide De Caro, Gennaro Di Meo, Valeria Cardellini, Salvatore Filippone, Francesco Lo Presti, Francesco Silvestri, Paolo Palazzari, Stefania Perri
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures. CoRR (2023)
Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Stefania Perri, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke
A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. CoRR (2023)
Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Andrea Mineo, Giuseppe Ascia, Vincenzo Catania
DNN Model Compression for IoT Domain-Specific Hardware Accelerators. IEEE Internet Things J. 9 (9) (2022)
Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Habiba Lahdhiri, Giuseppe Ascia, Vincenzo Catania
Exploiting the Approximate Computing Paradigm with DNN Hardware Accelerators. MECO (2022)
Enrico Russo, Maurizio Palesi, Davide Patti, Habiba Lahdhiri, Salvatore Monteleone, Giuseppe Ascia, Vincenzo Catania
Combined Application of Approximate Computing Techniques in DNN Hardware Accelerators. IPDPS Workshops (2022)
Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Vincenzo Catania
MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping. DATE (2022)
Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Vincenzo Catania
LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation. PerCom Workshops (2021)
Giuseppe Ascia, Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti
Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression. NOCS (2020)
Giuseppe Ascia, Vincenzo Catania, John Jose, Salvatore Monteleone, Maurizio Palesi, Davide Patti
Improving Inference Latency and Energy of Network-on-Chip based Convolutional Neural Networks through Weights Compression. IPDPS Workshops (2020)
Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose, Valerio Mario Salerno
Exploiting Data Resilience in Wireless Network-on-chip Architectures. ACM J. Emerg. Technol. Comput. Syst. 16 (2) (2020)
Habiba Lahdhiri, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Jordane Lorandel, Emmanuelle Bourdel, Vincenzo Catania
DNNZip: Selective Layers Compression Technique in Deep Neural Network Accelerators. DSD (2020)
Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose
Analyzing networks-on-chip based deep neural networks. NOCS (2019)
Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose
Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices. IoTSMS (2019)
Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose
Improving energy consumption of NoC based architectures through approximate communication. MECO (2018)
Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose
Approximate Wireless Networks-on-Chip. DCIS (2018)
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Partha Pratim Pande, Vincenzo Catania
On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (11) (2016)
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures. IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Giuseppe Ascia, Vincenzo Catania, Raffaele Di Natale, Andrea Fornaia, Misael Mongiovì, Salvatore Monteleone, Giuseppe Pappalardo, Emiliano Tramontana
Making Android Apps Data-Leak-Safe by Data Flow Analysis and Code Injection. WETICE (2016)
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
Exploiting antenna directivity in wireless NoC architectures. Microprocess. Microsystems 43 (2016)
Maurizio Palesi, Davide Patti, Giuseppe Ascia, Daniela Panno, Vincenzo Catania
Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip. J. Comput. Sci. 11 (3) (2015)
Andrea Mineo, Mohd Shahrizal Rusli, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures. DATE (2015)
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs. DATE (2014)
Mohd Shahrizal Rusli, Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono
A Closed Loop Control based Power Manager for WiNoC Architectures. MES (2014)
Alessandro G. Di Nuovo, Giuseppe Ascia
A fuzzy system index to preserve interpretability in deep tuning of fuzzy rule based classifiers. J. Intell. Fuzzy Syst. 25 (2) (2013)
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
NoC links energy reduction through link voltage scaling. ICSAMOS (2013)
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
Runtime Online Links Voltage Scaling for Low Energy Networks on Chip. DSD (2013)
Giuseppe Ascia, Maurizio Palesi, Vincenzo Catania
An Adaptive Output Selection Function Based on a Fuzzy Rule Base System for Network on Chip. DSD (2013)
Andrea Mineo, Marina Masi, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
Low Energy Mapping Techniques under Reliability and Bandwidth Constraints. HPCC/EUC (2013)
Alessandro G. Di Nuovo, Giuseppe Ascia, Vincenzo Catania
A Study on Evolutionary Multi-Objective Optimization with Fuzzy Approximation for Computational Expensive Problems. PPSN (2) (2012)
Maurizio Palesi, Giuseppe Ascia, Fabrizio Fazzino, Vincenzo Catania
Data Encoding Schemes in Networks on Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (5) (2011)
Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems. Appl. Soft Comput. 11 (1) (2011)
Maurizio Palesi, Fabrizio Fazzino, Giuseppe Ascia, Vincenzo Catania
Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. DSD (2009)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip. IEEE Trans. Computers 57 (6) (2008)
Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
Efficient design space exploration for application specific systems-on-a-chip. J. Syst. Archit. 53 (10) (2007)
Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design. IEEE Congress on Evolutionary Computation (2006)
Giuseppe Ascia, Vincenzo Catania, Daniela Panno
An integrated fuzzy-GA approach for buffer management. IEEE Trans. Fuzzy Syst. 14 (4) (2006)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. J. Univers. Comput. Sci. 12 (4) (2006)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks. ESTIMedia (2006)
Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania
Fuzzy decision making in embedded system design. CODES+ISSS (2006)
Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. ICSAMOS (2006)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
An evolutionary approach to network-on-chip mapping problem. Congress on Evolutionary Computation (2005)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (4) (2005)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
Exploring Design Space of VLIW Architectures. ASAP (2005)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. ASP-DAC (2005)
Giuseppe Ascia, Vincenzo Catania, Daniela Panno
An evolutionary management scheme in high-performance packet switches. IEEE/ACM Trans. Netw. 13 (2) (2005)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
Hyperblock formation: a power/energy perspective for high performance VLIW architectures. ISCAS (4) (2005)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
Multi-objective mapping for mesh-based NoC architectures. CODES+ISSS (2004)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
A GA-based design space exploration framework for parameterized system-on-a-chip platforms. IEEE Trans. Evol. Comput. 8 (4) (2004)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
Multi-objective Optimization of a Parameterized VLIW Architecture. Evolvable Hardware (2004)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
A Genetic Approach To Bus Encoding. VLSI-SOC (2003)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. PATMOS (2003)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato
An evolutionary approach for reducing the switching activity in address buses. IEEE Congress on Evolutionary Computation (2003)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. ESTIMedia (2003)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Antonio Parlato
An evolutionary approach for reducing the energy in address buses. ISICT (2003)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
A Framework for Design Space Exploration of Parameterized VLSI Systems. VLSI Design (2002)
Giuseppe Ascia, Vincenzo Catania, Daniela Panno
An efficient buffer management policy based on an integrated Fuzzy-GA approach. INFOCOM (2002)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms. VLSI-SOC (2001)
Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili, Daniela Panno
A Fuzzy Buffer Management Scheme For ATM and IP Networks. INFOCOM (2001)
Giuseppe Ascia, Vincenzo Catania, Daniela Panno
An adaptive fuzzy threshold scheme for high performance shared-memory switches. SAC (2001)
Giuseppe Ascia, Vincenzo Catania
A General Purpose Processor Oriented Fuzzy Reasoning. FUZZ-IEEE (2001)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Sarta
An Instruction-Level Power Analysis Model with Data Dependency. VLSI Design 2001 (2) (2001)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
Parameterised system design based on genetic algorithms. CODES (2001)
Giuseppe Ascia, Vincenzo Catania, Daniela Panno
An efficient fuzzy system for traffic management in high-speed packet-switched networks. Soft Comput. 5 (4) (2001)
Giuseppe Ascia, Vincenzo Catania
A pipeline parallel architecture for a fuzzy inference processor. FUZZ-IEEE (2000)
Giuseppe Ascia, Vincenzo Catania, Marco Russo
VLSI hardware architecture for complex fuzzy systems. IEEE Trans. Fuzzy Syst. 7 (5) (1999)
Giuseppe Ascia, Vincenzo Catania
An Optimized Parallel RISC Processor for Fuzzy Computing. Applied Informatics (1999)
Giuseppe Ascia, Vincenzo Catania
A Framework for a Parallel Architecture Dedicated to Soft Computing. VLSI Design (1998)
Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili, Sergio Palazzo, Daniela Panno
A VLSI fuzzy expert system for real-time traffic control in ATM networks. IEEE Trans. Fuzzy Syst. 5 (1) (1997)
Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili
Design of a VLSI Hardware PET Decoder. VLSI Design (1997)
Giuseppe Ascia, Vincenzo Catania, Antonio Puliafito, Lorenzo Vita
A Reconfigurable Parallel Architecture for a Fuzzy Processor. Inf. Sci. 88 (1-4) (1996)
Giuseppe Ascia, Vincenzo Catania
An Efficient Hardware Architecture to Support Complex Fuzzy Reasoning. Int. J. Artif. Intell. Tools 5 (1-2) (1996)
Giuseppe Ascia, Vincenzo Catania
Design of a VLSI parallel processor for fuzzy computing. VLSI Design (1995)
Giuseppe Ascia, Giuseppe Ficili, Daniela Panno
Design of a VLSI fuzzy processor for ATM traffic sources management. LCN (1995)
Giuseppe Ascia, Vincenzo Catania
An efficient hardware architecture to support complex fuzzy reasoning. ICTAI (1995)
Giuseppe Ascia, Vincenzo Catania, Biagio Giacalone, Marco Russo, Lorenzo Vita
Designing for parallel fuzzy computing. IEEE Micro 15 (6) (1995)
Vincenzo Catania, Giuseppe Ascia
A VLSI Parallel Architecture for Fuzzy Expert Systems. Int. J. Pattern Recognit. Artif. Intell. 9 (2) (1995)
Abraham Kandel, Giuseppe Ascia, Vincenzo Catania, Biagio Giacalone, Marco Russo, Lorenzo Vita, Andrés Jaramillo-Botero, Yoichi Miyake, Hua Harry Li, Nowell Godfrey, Yuandong Ji, Shuwei Guo, Liliane Peters, Krishna Rao Valavala, Mahmoud A. Manzoul, Antonio Ruiz, Julio Gutiérrez, Felipe Fernández
Fuzzy Hardware Challenges. IEEE Micro 15 (6) (1995)