Maurizio Palesi

ORCID

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 78

Top Venues

CoRR

DATE

Microprocess. Microsystems

IEEE Trans. Computers

Publications

Francesco Giulio Blanco, Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania
Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems. CoRR (2024)
Elio Vinciguerra, Enrico Russo, Maurizio Palesi, Giuseppe Ascia, Hamaad Rafique
Improving LSTM-based Indoor Positioning via Simulation-Augmented Geomagnetic Field Dataset. MOST (2024)
Enrico Russo, Francesco Giulio Blanco, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Vincenzo Catania
Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning. ISCAS (2024)
Minghua Tang, Enrico Russo, Maurizio Palesi
Correction to: The position-based compression techniques for DNN model. J. Supercomput. 80 (1) (2024)
Abhijit Das, Enrico Russo, Maurizio Palesi
Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-Based Accelerators. IEEE Trans. Computers 73 (8) (2024)
Enrico Russo, Francesco Giulio Blanco, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Vincenzo Catania
Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning. CoRR (2024)
Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania
Attention-Based Deep Reinforcement Learning for Qubit Allocation in Modular Quantum Architectures. CoRR (2024)
Marco Finocchiaro, Salvatore Monteleone, Enrico Russo, Maurizio Palesi, Davide Patti
Lessons Learned on the Design of Cost-Effective and Highly Compatible Smart Gloves. MECO (2024)
Eduard Alarcón, Sergi Abadal, Fabio Sebastiano, Masoud Babaie, Edoardo Charbon, Peter Haring Bolívar, Maurizio Palesi, Elena Blokhina, Dirk Leipold, Robert Bogdan Staszewski, Artur García-Sáez, Carmen G. Almudéver
Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package. CoRR (2023)
Grazia Veronica Aiosa, Maurizio Palesi, Francesca Sapuppo, Maria Gabriella Xibilia
Explainable AI-Based Clinical Decision Support System for Obesity Comorbidity Analysis. e-Science (2023)
Maurizio Palesi, Enrico Russo, Abhijit Das, John Jose
Wireless enabled Inter-Chiplet Communication in DNN Hardware Accelerators. IPDPS Workshops (2023)
Enrico Russo, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Salvatore Monteleone, Vincenzo Catania
Memory-Aware DNN Algorithm-Hardware Mapping via Integer Linear Programming. CF (2023)
Grazia Veronica Aiosa, Maurizio Palesi, Francesca Sapuppo
EXplainable AI for Decision Support to Obesity Comorbidities Diagnosis. IEEE Access 11 (2023)
Enrico Russo, Maurizio Palesi, Davide Patti, Salvatore Monteleone, Giuseppe Ascia, Vincenzo Catania
Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators. IEEE Internet Things J. 10 (2) (2023)
Hamaad Rafique, Davide Patti, Maurizio Palesi, Vincenzo Catania
m-BMC: Exploration of Magnetic Field Measurements for Indoor Positioning Using mini-Batch Magnetometer Calibration. MOST (2023)
Fabrizio Ferrandi, Serena Curzel, Leandro Fiorin, Daniele Ielmini, Cristina Silvano, Francesco Conti, Alessio Burrello, Francesco Barchi, Luca Benini, Luciano Lavagno, Teodoro Urso, Enrico Calore, Sebastiano Fabio Schifano, Cristian Zambelli, Maurizio Palesi, Giuseppe Ascia, Enrico Russo, Nicola Petra, Davide De Caro, Gennaro Di Meo, Valeria Cardellini, Salvatore Filippone, Francesco Lo Presti, Francesco Silvestri, Paolo Palazzari, Stefania Perri
A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures. CoRR (2023)
Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Stefania Perri, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke
A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. CoRR (2023)
Eduard Alarcón, Sergi Abadal, Fabio Sebastiano, Masoud Babaie, Edoardo Charbon, Peter Haring Bolívar, Maurizio Palesi, Elena Blokhina, Dirk Leipold, Robert Bogdan Staszewski, Artur García-Sáez, Carmen G. Almudéver
Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package. ISCAS (2023)
Minghua Tang, Enrico Russo, Maurizio Palesi
The position-based compression techniques for DNN model. J. Supercomput. 79 (15) (2023)
Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Andrea Mineo, Giuseppe Ascia, Vincenzo Catania
DNN Model Compression for IoT Domain-Specific Hardware Accelerators. IEEE Internet Things J. 9 (9) (2022)
Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Habiba Lahdhiri, Giuseppe Ascia, Vincenzo Catania
Exploiting the Approximate Computing Paradigm with DNN Hardware Accelerators. MECO (2022)
Abhijit Das, Abhishek Kumar, John Jose, Maurizio Palesi
Revising NoC in Future Multicore-Based Consumer Electronics for Performance. IEEE Consumer Electron. Mag. 11 (3) (2022)
Chixiao Chen, Jieming Yin, Yarui Peng, Maurizio Palesi, Wenxu Cao, Letian Huang, Amit Kumar Singh, Haocong Zhi, Xiaohang Wang
Design Challenges of Intrachiplet and Interchiplet Interconnection. IEEE Des. Test 39 (6) (2022)
Enrico Russo, Maurizio Palesi, Davide Patti, Habiba Lahdhiri, Salvatore Monteleone, Giuseppe Ascia, Vincenzo Catania
Combined Application of Approximate Computing Techniques in DNN Hardware Accelerators. IPDPS Workshops (2022)
Giuliano Canzonieri, Salvatore Monteleone, Maurizio Palesi, Enrico Russo, Davide Patti
Analyzing the Impact of DNN Hardware Accelerators-Oriented Compression Techniques on General-Purpose Low-End Boards. MobiWIS (2022)
Abhijit Das, Enrico Russo, Maurizio Palesi
Multi-Objective Hardware-Mapping Co-Optimisation for Multi-Tenant DNN Accelerators. CoRR (2022)
Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Vincenzo Catania
MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping. DATE (2022)
Dipika Deb, John Jose, Maurizio Palesi
COPE: Reducing Cache Pollution and Network Contention by Inter-tile Coordinated Prefetching in NoC-based MPSoCs. ACM Trans. Design Autom. Electr. Syst. 26 (3) (2021)
Siyuan Xiao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Liang Wang, Terrence S. T. Mak
On Performance Optimization and Quality Control for Approximate-Communication-Enabled Networks-on-Chip. IEEE Trans. Computers 70 (11) (2021)
Haocong Zhi, Xianuo Xu, Weijian Han, Zhilin Gao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Letian Huang
A Methodology for Simulating Multi-chiplet Systems Using Open-source Simulators. NANOCOM (2021)
Enrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Vincenzo Catania
LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation. PerCom Workshops (2021)
Nizar Dahir, Ammar Karkar, Maurizio Palesi, Terrence S. T. Mak, Alex Yakovlev
Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach. Integr. 81 (2021)
Abhijit Das, Abhishek Kumar, John Jose, Maurizio Palesi
Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty. IEEE Trans. Computers 70 (6) (2021)
Giuseppe Ascia, Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti
Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression. NOCS (2020)
Andrea Mineo, Maurizio Palesi, Davide Patti, Vincenzo Catania
Cloud-Based Energy Efficient Scheme for Sigfox Monarch as Asset Tracking Service. COINS (2020)
Fangyang Shen, Mei Yang, Maurizio Palesi
Introduction to the special section on intelligent computing systems and their applications. Comput. Electr. Eng. 85 (2020)
Abhijit Das, Abhishek Kumar, John Jose, Maurizio Palesi
Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-processors. ISVLSI (2020)
Jordane Lorandel, Habiba Lahdhiri, Emmanuelle Bourdel, Salvatore Monteleone, Maurizio Palesi
Efficient Compression Technique for NoC-based Deep Neural Network Accelerators. DSD (2020)
Seyed Morteza Nabavinejad, Mohammad Baharloo, Kun-Chih Chen, Maurizio Palesi, Tim Kogel, Masoumeh Ebrahimi
An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 10 (3) (2020)
Giuseppe Ascia, Vincenzo Catania, John Jose, Salvatore Monteleone, Maurizio Palesi, Davide Patti
Improving Inference Latency and Energy of Network-on-Chip based Convolutional Neural Networks through Weights Compression. IPDPS Workshops (2020)
Kun-Chih Chen, Masoumeh Ebrahimi, Maurizio Palesi, Tim Kogel
Guest Editorial: Communication-Aware Designs and Methodologies for Reliable and Adaptable On-Chip AI SubSystems and Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 10 (3) (2020)
Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose, Valerio Mario Salerno
Exploiting Data Resilience in Wireless Network-on-chip Architectures. ACM J. Emerg. Technol. Comput. Syst. 16 (2) (2020)
Maurizio Palesi, Kun-Chih Jimmy Chen, Midia Reshadi
Special issue on energy-efficient many-core embedded systems and architectures (SI: NoCArc18). J. Syst. Archit. 109 (2020)
Habiba Lahdhiri, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Jordane Lorandel, Emmanuelle Bourdel, Vincenzo Catania
DNNZip: Selective Layers Compression Technique in Deep Neural Network Accelerators. DSD (2020)
Alireza Monemi, Farshad Khunjush, Maurizio Palesi, Hamid Sarbazi-Azad
An Enhanced Dynamic Weighted Incremental Technique for QoS Support in NoC. ACM Trans. Parallel Comput. 7 (2) (2020)
Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti
Impact of Users' Beliefs in Text-Based Linguistic Interaction. IEEE Access 8 (2020)
Sirine Mnejja, Yassine Aydi, Mohamed Abid, Salvatore Monteleone, Maurizio Palesi, Davide Patti
Implementing On-Chip Wireless Communication in Multi-stage Interconnection NoCs. AINA (2020)
Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose
Analyzing networks-on-chip based deep neural networks. NOCS (2019)
Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose
Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices. IoTSMS (2019)
Dipika Deb, John Jose, Maurizio Palesi
ECAP: energy-efficient caching for prefetch blocks in tiled chip multiprocessors. IET Comput. Digit. Tech. 13 (6) (2019)
Dipika Deb, John Jose, Maurizio Palesi
Performance Enhancement of Caches in TCMPs Using Near Vicinity Prefetcher. VLSI Design (2019)
Siyuan Xiao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Terrence S. T. Mak
ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip. DATE (2019)
Minghua Tang, Maurizio Palesi
Study on logic-based routing for 3D NOCs. NoCArc@MICRO (2019)
Sarzamin Khan, Sheraz Anjum, Usman Ali Gulzari, Farruh Ishmanov, Maurizio Palesi, Muhammad Khalil Afzal
An optimized hybrid algorithm in term of energy and performance for mapping real time workloads on 2d based on-chip networks. Appl. Intell. 48 (12) (2018)
Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose
Improving energy consumption of NoC based architectures through approximate communication. MECO (2018)
Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti
Packetization of Shared-Memory Traces for Message Passing Oriented NoC Simulation. ISC (2018)
Simi Zerine Sleeba, John Jose, Maurizio Palesi, Rekha K. James, Maniyelil Govindankutty Mini
Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip. VLSI-SoC (2018)
Abhijit Das, Sarath Babu, John Jose, Sangeetha Jose, Maurizio Palesi
Critical Packet Prioritisation by Slack-Aware Re-Routing in On-Chip Networks. NOCS (2018)
Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti
Improving Energy Efficiency in Wireless Network-on-Chip Architectures. ACM J. Emerg. Technol. Comput. Syst. 14 (1) (2018)
Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose
Approximate Wireless Networks-on-Chip. DCIS (2018)
Minghua Tang, Jing Lin, Maurizio Palesi
The Suboptimal Routing Algorithm for 2D Mesh Network. IEEE Trans. Computers 67 (5) (2018)
Salvatore Michele Biondi, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti
smARTworks: A Multi-sided Context-aware Platform for the Smart Museum. PECCS (2018)
Erwan Moreac, Johann Laurent, Pierre Bomel, André Rossi, Emmanuel Boutillon, Maurizio Palesi
Energy aware Networks-on-Chip cortex inspired communication. PATMOS (2017)
Alireza Monemi, Jia Wei Tang, Maurizio Palesi, Muhammad N. Marsono
ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform. Microprocess. Microsystems 54 (2017)
Minghua Tang, Xiaola Lin, Maurizio Palesi
The Repetitive Turn Model for Adaptive Routing. IEEE Trans. Computers 66 (1) (2017)
Alireza Monemi, Chia Yee Ooi, Maurizio Palesi, Muhammad N. Marsono
Ping-lock round robin arbiter. Microelectron. J. 63 (2017)
Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti
Improving the energy efficiency of wireless Network on Chip architectures through online selective buffers and receivers shutdown. CCNC (2016)
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Partha Pratim Pande, Vincenzo Catania
On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (11) (2016)
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures. IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Fangyang Shen, Maurizio Palesi, Mei Yang
Introduction to the special section on "Sustainable processor architectures and applications". Microprocess. Microsystems 46 (2016)
Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti
Cycle-Accurate Network on Chip Simulation with Noxim. ACM Trans. Model. Comput. Simul. 27 (1) (2016)
Minghua Tang, Xiaola Lin, Maurizio Palesi
Local Congestion Avoidance in Network-on-Chip. IEEE Trans. Parallel Distributed Syst. 27 (7) (2016)
Maurizio Palesi, Mario Collotta, Masoud Daneshtalab, Pradip Bose
Special issue on energy efficient methods and systems in the emerging cloud era. J. Comput. Syst. Sci. 82 (2) (2016)
Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono, Maurizio Palesi
Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC. NoCArc@MICRO (2016)
Amin Rezaei, Masoud Daneshtalab, Maurizio Palesi, Danella Zhao
Efficient Congestion-Aware Scheme for Wireless on-Chip Networks. PDP (2016)
Mohamed Bakhouya, Masoud Daneshtalab, Maurizio Palesi, Hassan Ghasemzadeh
Many-core System-on-Chip: architectures and applications. Microprocess. Microsystems 43 (2016)
Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti
Energy efficient transceiver in wireless Network on Chip architectures. DATE (2016)
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
Exploiting antenna directivity in wireless NoC architectures. Microprocess. Microsystems 43 (2016)
Fangyang Shen, Lingjia Liu, Maurizio Palesi
Introduction to the special issue on "Emerging research in Internet of Things". Comput. Electr. Eng. 44 (2015)
Masoud Daneshtalab, Maurizio Palesi, Terrence S. T. Mak
Introduction to the special issue on NoC-based many-core architectures. Comput. Electr. Eng. 45 (2015)
Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti
Noxim: An open, extensible and cycle-accurate network on chip simulator. ASAP (2015)
Minghua Tang, Xiaola Lin, Maurizio Palesi
An Offline Method for Designing Adaptive Routing Based on Pressure Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (2) (2015)
Minghua Tang, Xiaola Lin, Maurizio Palesi
Routing Pressure: A Channel-Related and Traffic-Aware Metric of Routing Algorithm. IEEE Trans. Parallel Distributed Syst. 26 (3) (2015)
Hyunok Oh, Muhammad Shafique, Todor P. Stefanov, Maurizio Palesi
Message from the Chairs. ESTIMedia (2015)
Maurizio Palesi, Davide Patti, Giuseppe Ascia, Daniela Panno, Vincenzo Catania
Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip. J. Comput. Sci. 11 (3) (2015)
Andrea Mineo, Mohd Shahrizal Rusli, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures. DATE (2015)
Nima Jafarzadeh, Maurizio Palesi, Saeedeh Eskandari, Shaahin Hessabi, Ali Afzali-Kusha
Low Energy yet Reliable Data Communication Scheme for Network-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (12) (2015)
Masoud Daneshtalab, Maurizio Palesi, Terrence S. T. Mak
Introduction to the Special Issue on Network-on-Chip Architectures. Comput. Electr. Eng. 40 (8) (2014)
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs. DATE (2014)
Davide Patti, Maurizio Palesi, Vincenzo Catania
Merging Compilation and Microarchitectural Configuration Spaces for Performance/Power Optimization in VLIW-Based Systems. CSOC (2014)
Maurizio Palesi, Todor P. Stefanov
Editorial: Special Section on ESTIMedia'13. ACM Trans. Embed. Comput. Syst. 13 (3s) (2014)
Mohammad Fattah, Maurizio Palesi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems. DAC (2014)
Masoud Daneshtalab, Maurizio Palesi, Juha Plosila
Editorial: Special issue on design challenges for many-core processors. ACM Trans. Embed. Comput. Syst. 13 (3s) (2014)
Xiaohang Wang, Baoxin Zhao, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi
Adaptive power allocation for many-core systems inspired from multiagent auction model. DATE (2014)
Xiaohang Wang, Mei Yang, Yingtao Jiang, Peng Liu, Masoud Daneshtalab, Maurizio Palesi, Terrence S. T. Mak
On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. ACM Trans. Embed. Comput. Syst. 13 (2s) (2014)
Masoud Daneshtalab, Maurizio Palesi, Juha Plosila, Ahmed Hemani
Special issue on many-core embedded systems. Microprocess. Microsystems 38 (6) (2014)
Mohd Shahrizal Rusli, Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania, Muhammad N. Marsono
A Closed Loop Control based Power Manager for WiNoC Architectures. MES (2014)
Nima Jafarzadeh, Maurizio Palesi, Ahmad Khademzadeh, Ali Afzali-Kusha
Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Xiaohang Wang, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi
On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. NOCS (2013)
Todor P. Stefanov, Maurizio Palesi, Jian-Jia Chen, Jörg Henkel
Message from the chairs. ESTIMedia (2013)

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Publication Activity (10 Years)

Top Topics

Top Venues

Maurizio Palesi