Chia Yee Ooi

Publication Activity (10 Years)

Years Active: 2004-2022
Publications (10 Years): 21

Top Topics

Supervised Learning

Pectoral Muscle

Fault Detection

Top Venues

Artif. Intell. Rev.

Publications

Chong Yeam Tan, Chia Yee Ooi, Hau Sim Choo, Nordinah Ismail
Efficient hardware-accelerated pseudoinverse computation through algorithm restructuring for parallelization in high-level synthesis. Int. J. Circuit Theory Appl. 50 (2) (2022)
Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono
An FPGA-based IP Core Subscription-Oriented Fog Computing Platform. IPDPS Workshops (2022)
Tze Hon Tan, Chia Yee Ooi, Muhammad Nadzir Marsono
RtFog: A Real-Time FPGA-Based Fog Node With Remote Dynamically Reconfigurable Application Plane for Fog Analytics Redeployment. IEEE Trans. Green Commun. Netw. 6 (1) (2022)
Tariq Ibrahim Al-Shwaheen, Mehrdad Moghbel, Yuan Wen Hau, Chia Yee Ooi
Use of learning approaches to predict clinical deterioration in patients based on various variables: a review of the literature. Artif. Intell. Rev. 55 (2) (2022)
Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono
An FPGA-based Middlebox with Remote Dynamically Reconfigurable Application Plane. TENCON (2021)
Hau Sim Choo, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail, Mehrdad Moghbel, Chee Hoo Kok
Register-Transfer-Level Features for Machine-Learning-Based Hardware Trojan Detection. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2020)
Mehrdad Moghbel, Chia Yee Ooi, Nordinah Ismail, Yuan Wen Hau, Nogol Memari
A review of breast boundary and pectoral muscle segmentation methods in computer-aided detection/diagnosis of breast mammography. Artif. Intell. Rev. 53 (3) (2020)
Chee Hoo Kok, Chia Yee Ooi, Mehrdad Moghbel, Nordinah Ismail, Hau Sim Choo, Michiko Inoue
Classification of Trojan Nets Based on SCOAP Values using Supervised Learning. ISCAS (2019)
Chee Hoo Kok, Chia Yee Ooi, Michiko Inoue, Mehrdad Moghbel, Sreedharan Baskara Dass, Hau Sim Choo, Nordinah Ismail, Fawnizu Azmadi Hussin
Net Classification Based on Testability and Netlist Structural Features for Hardware Trojan Detection. ATS (2019)
Pyi Phyo Aung, Koichiro Mashiko, Nordinah Binti Ismail, Chia Yee Ooi
Evaluation of SRAM PUF Characteristics and Generation of Stable Bits for IoT Security. IRICT (2019)
Chong Yeam Tan, Chia Yee Ooi, Nordinah Ismail
Loop Optimizations of MGS-QRD Algorithm for FPGA High-Level Synthesis. SoCC (2019)
Hau Sim Choo, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail, Mehrdad Moghbel, Sreedharan Baskara Dass, Chee Hoo Kok, Fawnizu Azmadi Hussin
Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level. ATS (2019)
Tze Hon Tan, Chia Yee Ooi, Muhammad Nadzir Marsono
drDRM: A PUF-Based Dynamically Reconfigurable DRM Mechanism for FPGA-Based Platform. CANDAR (2018)
Mahshid Mojtabavi Naeini, Sreedharan Baskara Dass, Chia Yee Ooi, Tomokazu Yoneda, Michiko Inoue
An integrated DFT solution for power reduction in scan test applications by low power gating scan cell. Integr. 57 (2017)
Jeevan Sirkunan, Chia Yee Ooi, Nasir Shaikh-Husin, Yuan Wen Hau, Muhammad N. Marsono
Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms. J. Syst. Archit. 73 (2017)
Alireza Monemi, Chia Yee Ooi, Maurizio Palesi, Muhammad N. Marsono
Ping-lock round robin arbiter. Microelectron. J. 63 (2017)
Tze Hon Tan, Chia Yee Ooi, Muhammad Nadzir Marsono
hpFog: A FPGA-Based Fog Computing Platform. NAS (2017)
Nurita Mohamad, Chia Yee Ooi, Nordinah Bt Ismail, Jwing Teh
SVA checker generator for FPGA-based verification platform. ISCAS (2016)
Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono, Maurizio Palesi
Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC. NoCArc@MICRO (2016)
Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono
A modular architecture for dynamically reconfigurable middlebox with customized reconfiguration handler. FPT (2016)
Ayub Chin Abdullah, Chia Yee Ooi, Nordinah Bt Ismail, Nurita Binti Mohammad
Power-aware through-silicon-via minimization by partitioning finite state machine with datapath. ISCAS (2016)
Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono
Virtual Channel and Switch Allocation for Low Latency Network-on-Chip Routers. FCCM (2015)
Mahdieh Nadi Senejani, Mahdiar Hosein Ghadiry, Chia Yee Ooi, Muhammad Nadzir Marsono
Built-in Self Test Power and Test Time Analysis in On-chip Networks. Circuits Syst. Signal Process. 34 (4) (2015)
Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono
rrBox: A remote dynamically reconfigurable network processing middlebox. FPL (2015)
Mahshid Mojtabavi Naeini, Chia Yee Ooi
A Novel Scan Architecture for Low Power Scan-Based Testing. VLSI Design 2015 (2015)
Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono
Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique. Int. J. Reconfigurable Comput. 2015 (2015)
Jeevan Sirkunan, Chia Yee Ooi, Muhammad N. Shaikh-Husin, Yuan Wen Hau, Muhammad N. Marsono
Adaptive Configurable Transactional Memory for Multi-processor FPGA Platforms. FCCM (2015)
Jeevan Sirkunan, Chia Yee Ooi, Nasir Shaikh-Husin, Yuan Wen Hau, Muhammad Nadzir Marsono
Hardware transactional memory on multi-processor FPGA platform. ISCAS (2014)
Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono
rrBox: A Remote Dynamically Reconfigurable Middlebox for Network Protection. CANDAR (2014)
Tze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono
rrBox: Remote dynamically reconfigurable middlebox using NetFPGA. ISCIT (2014)
Hasliza Hassan, Chia Yee Ooi
Thermal Model with Metal Consideration for System-on-Chip Testing. J. Low Power Electron. 10 (3) (2014)
Tze Hon Tan, Chia Yee Ooi, Yuan Wen Hau, Nasir Shaikh-Husin, Muhammad N. Marsono
Remote dynamically reconfigurable platform using NetFPGA. ISCAS (2014)
Ling Kim Loo, Chia Yee Ooi, V. Y. Liew, Yuan Wen Hau, Muhammad N. Marsono
Packet logging mechanism for adaptive online fault detection on Network-on-Chip. ISCAS (2014)
Sieng Wong, Chia Yee Ooi, Yuan Wen Hau, Muhammad N. Marsono, Nasir Shaikh-Husin
Feasible transition path generation for EFSM-based system testing. ISCAS (2013)
Mahdieh Nadi Senjani, Mahdiar Hosein Ghadiry, Chia Yee Ooi, Muhammad N. Marsono
A Semi-Analytical Approach to Study the Energy Consumption of On-Chip Networks Testing. J. Low Power Electron. 9 (2) (2013)
Chia Yee Ooi, Jia Pao Sua, Siaw Chen Lee
Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm. Comput. Electr. Eng. 38 (6) (2012)
Chia Yee Ooi, Hideo Fujiwara
A New Design-for-Testability Method Based on Thru-Testability. J. Electron. Test. 27 (5) (2011)
Yuan Wen Hau, Muhammad N. Marsono, Chia Yee Ooi, Mohamed Khalil Hani
A Network-on-Chip simulation framework for homogeneous Multi-Processor System-on-Chip. ASICON (2011)
Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (9) (2008)
Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara
-Notation. IEICE Trans. Inf. Syst. (8) (2007)
Chia Yee Ooi, Hideo Fujiwara
A New Scan Design Technique Based on Pre-Synthesis Thru Functions. ATS (2006)
Chia Yee Ooi, Hideo Fujiwara
A New Class of Sequential Circuits with Acyclic Test Generation Complexity. ICCD (2006)
Chia Yee Ooi, Thomas Clouqueur, Hideo Fujiwara
Notation and Its Applications. IEICE Trans. Inf. Syst. (12) (2005)
Chia Yee Ooi, Hideo Fujiwara
Classification of Sequential Circuits Based on ?k Notation. Asian Test Symposium (2004)