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An integrated DFT solution for power reduction in scan test applications by low power gating scan cell.
Mahshid Mojtabavi Naeini
Sreedharan Baskara Dass
Chia Yee Ooi
Tomokazu Yoneda
Michiko Inoue
Published in:
Integr. (2017)
Keyphrases
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low power
power reduction
power consumption
low cost
high speed
power dissipation
power saving
low power consumption
digital signal processing
pattern recognition
energy efficiency
cmos technology
logic circuits
image sensor