Tomokazu Yoneda

Publication Activity (10 Years)

Years Active: 2001-2017
Publications (10 Years): 7

Top Topics

Memory Hierarchy

Pipelined Architecture

Asynchronous Cellular Automata

Top Venues

IEICE Trans. Inf. Syst.

Publications

Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue, Alex Orailoglu
Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions. ETS (2017)
Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue
An Effective and Sensitive Scan Segmentation Technique for Detecting Hardware Trojan. IEICE Trans. Inf. Syst. (1) (2017)
Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue, Alex Orailoglu
Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection. ATS (2017)
Mahshid Mojtabavi Naeini, Sreedharan Baskara Dass, Chia Yee Ooi, Tomokazu Yoneda, Michiko Inoue
An integrated DFT solution for power reduction in scan test applications by low power gating scan cell. Integr. 57 (2017)
Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue
Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair. IEICE Trans. Inf. Syst. (10) (2016)
Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue
Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC. ETS (2016)
Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato
An ECC-based memory architecture with online self-repair capabilities for reliability enhancement. ETS (2015)
Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue
Memory block based scan-BIST architecture for application-dependent FPGA testing. FPGA (2014)
Yussuf Ali, Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue
Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units. ATS (2014)
Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura
DART: Dependable VLSI test architecture and its implementation. ITC (2012)
Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
A Failure Prediction Strategy for Transistor Aging. IEEE Trans. Very Large Scale Integr. Syst. 20 (11) (2012)
Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue
A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation. ITC (2012)
Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hideo Fujiwara
Test Pattern Ordering and Selection for High Quality Test Set under Constraints. IEICE Trans. Inf. Syst. (12) (2012)
Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda
Delay Testing: Improving Test Quality and Avoiding Over-testing. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara
Temperature-Variation-Aware Test Pattern Optimization. ETS (2011)
Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara
Balanced Secure Scan: Partial Scan Approach for Secret Information Protection. J. Electron. Test. 27 (2) (2011)
Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara
Faster-than-at-speed test for increased test quality and in-field reliability. ITC (2011)
Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara
Test pattern selection to optimize delay test quality with a limited size of test set. ETS (2010)
Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara
Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. VTS (2010)
Fawnizu Azmadi Hussin, Thomas Edison Yu, Tomokazu Yoneda, Hideo Fujiwara
RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC. APCCAS (2010)
Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
Design and Optimization of Transparency-Based TAM for SoC Test. IEICE Trans. Inf. Syst. (6) (2010)
Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
Aging test strategy and adaptive test scheduling for SoC failure prediction. IOLTS (2010)
Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara
Seed Ordering and Selection for High Quality Delay Test. Asian Test Symposium (2010)
Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. ASP-DAC (2009)
Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara
Partial Scan Approach for Secret Information Protection. ETS (2009)
Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips. IEICE Trans. Inf. Syst. (10) (2008)
Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint. IEICE Trans. Inf. Syst. (3) (2008)
Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints. IEICE Trans. Inf. Syst. (3) (2008)
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time. IEICE Trans. Inf. Syst. (7) (2008)
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints. IEICE Trans. Inf. Syst. (7) (2008)
Tomokazu Yoneda, Hideo Fujiwara
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects. DATE (2008)
Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths. ATS (2008)
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara
Scheduling Power-Constrained Tests through the SoC Functional Bus. IEICE Trans. Inf. Syst. (3) (2008)
Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (9) (2008)
Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers. DATE (2007)
Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
TAM Design and Optimization for Transparency-Based SoC Test. VTS (2007)
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. ASP-DAC (2007)
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing. ATS (2007)
Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara
A DFT Method for Time Expansion Model at Register Transfer Level. DAC (2007)
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. ETS (2007)
Tomokazu Yoneda, Yuusuke Fukuda, Hideo Fujiwara
Test Scheduling for Memory Cores with Built-In Self-Repair. ATS (2007)
Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara
Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing. ISCAS (2007)
Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip. ATS (2007)
Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. VTS (2007)
Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara
A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips. IEICE Trans. Inf. Syst. (4) (2006)
Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
Power-constrained test scheduling for multi-clock domain SoCs. DATE (2006)
Tomokazu Yoneda, Hideo Fujiwara
Design for consecutive transparency method of RTL circuits. Systems and Computers in Japan 37 (2) (2006)
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara
Power-Constrained SOC Test Schedules through Utilization of Functional Buses. ICCD (2006)
Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara
A memory grouping method for sharing memory BIST logic. ASP-DAC (2006)
Tomokazu Yoneda, Hisakazu Takakuwa, Hideo Fujiwara
Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability. Asian Test Symposium (2005)
Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. Asian Test Symposium (2005)
Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard
An efficient scan tree design for test time reduction. ETS (2004)
Tomokazu Yoneda, Tetsuo Uchiyama, Hideo Fujiwara
Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability. ITC (2003)
Tomokazu Yoneda, Hideo Fujiwara
Design for Consecutive Transparency of Cores in System-on-a-Chip. VTS (2003)
Tomokazu Yoneda, Hideo Fujiwara
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores. J. Electron. Test. 18 (4-5) (2002)
Tomokazu Yoneda, Hideo Fujiwara
A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability. Asian Test Symposium (2001)