Seiji Kajihara

Publication Activity (10 Years)

Years Active: 1991-2022
Publications (10 Years): 29

Top Venues

ATS

ITC-Asia

IEEE Trans. Very Large Scale Integr. Syst.

IEICE Trans. Inf. Syst.

Publications

Kazuya Loki, Yasuyuki Kai, Kohei Miyase, Seiji Kajihara
A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications. ITC (2022)
Takaaki Kato, Yousuke Miyake, Seiji Kajihara
On Correction of A Delay Value Using Ring-Oscillators for Aging Detection and Prediction. ATS (2022)
Taiki Utsunomiya, Ryu Hoshino, Kohei Miyase, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara
Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits. ITC-Asia (2022)
Poki Chen, Joshua Adiel Wijaya, Seiji Kajihara, Trio Adiono, Hsiang-Yu Chen, Ruei-Ting Wang, Yousuke Miyake
A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection. IEEE Access 10 (2022)
Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian
On the Efficacy of Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption. IEICE Trans. Inf. Syst. (6) (2021)
Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Yukiya Miura, Smith Lai, Gavin Hung, Harry H. Chen, Haruo Kobayashi, Kazumi Hatayama
Innovative Test Practices in Asia. VTS (2020)
Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yukiya Miura
On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test. IOLTS (2020)
Poki Chen, Jian-Ting Lan, Ruei-Ting Wang, Nguyen My Qui, John Carl Joel S. Marquez, Seiji Kajihara, Yousuke Miyake
High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters. IEEE Trans. Very Large Scale Integr. Syst. 28 (4) (2020)
Masayuki Gondo, Yousuke Miyake, Takaaki Kato, Seiji Kajihara
On Evaluation for Aging-Tolerant Ring Oscillators with Accelerated Life Test And Its Application to A Digital Sensor. ATS (2020)
Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen
A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips. IEEE Trans. Emerg. Top. Comput. 8 (3) (2020)
Yousuke Miyake, Takaaki Kato, Seiji Kajihara
Path Delay Measurement with Correction for Temperature And Voltage Variations. ITC-Asia (2020)
Yousuke Miyake, Seiji Kajihara, Poki Chen
On-Chip Test Clock Validation Using A Time-to-Digital Converter in FPGAs. ITC-Asia (2019)
Shoi Tachibana, Shunsuke Araki, Seiji Kajihara, Shigeyuki Azuchi, Yukishige Nakajo, Hideki Shoda
FPGA implementation of ECDSA for Blockchain. ICCE-TW (2019)
Yousuke Miyake, Yasuo Sato, Seiji Kajihara
On-Chip Delay Measurement for In-Field Test of FPGAs. PRDC (2019)
Kohei Miyase, Yudai Kawano, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara
A Static Method for Analyzing Hotspot Distribution on the LSI. ITC-Asia (2019)
Yousuke Miyake, Yasuo Sato, Seiji Kajihara
A Selection Method of Ring Oscillators for An On-Chip Digital Temperature And Voltage Sensor. ITC-Asia (2019)
Shigeyuki Oshima, Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara
On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST. ATS (2018)
Takeru Nishimi, Yasuo Sato, Seiji Kajihara, Yoshiyuki Nakamura
Good Die Prediction Modelling from Limited Test Items. ITC-Asia (2018)
Yucong Zhang, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Hans-Joachim Wunderlich, Jun Qian
Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing. ATS (2018)
Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian
Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption. ATS (2017)
Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen
Analysis and mitigation or IR-Drop induced scan shift-errors. ITC (2017)
Yousuke Miyake, Yasuo Sato, Seiji Kajihara
On the effects of real time and contiguous measurement with a digital temperature and voltage sensor. ITC-Asia (2017)
Stefan Holst, Eric Schneider, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Hans-Joachim Wunderlich, Michael A. Kochte
Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test. ATS (2016)
Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen
A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST. ATS (2016)
Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura
Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor. IEEE Trans. Very Large Scale Integr. Syst. 24 (11) (2016)
Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara
Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
K. Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, J. Qian
Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. ATS (2015)
Senling Wang, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi
Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip. J. Low Power Electron. 11 (4) (2015)
Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
Identification of high power consuming areas with gate type and logic level information. ETS (2015)
Seiji Kajihara, Yousuke Miyake, Yasuo Sato, Yukiya Miura
An On-Chip Digital Environment Monitor for Field Test. ATS (2014)
Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura
Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test. ATS (2014)
Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. IEICE Trans. Inf. Syst. (10) (2014)
Yasuo Sato, Masafumi Monden, Yousuke Miyake, Seiji Kajihara
Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA. PRDC (2014)
Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume, Seiji Kajihara
Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories. ATS (2014)
Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. Asian Test Symposium (2013)
Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang
On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. VLSI Design (2013)
Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase
Scan-Out Power Reduction for Logic BIST. IEICE Trans. Inf. Syst. (9) (2013)
Yasuo Sato, Seiji Kajihara
A Stochastic Model for NBTI-Induced LSI Degradation in Field. Asian Test Symposium (2013)
Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
Search Space Reduction for Low-Power Test Generation. Asian Test Symposium (2013)
Yuta Yamato, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen, Laung-Terng Wang, Michael A. Kochte
LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing. IEEE Des. Test 30 (4) (2013)
Kohei Miyase, Ryota Sakai, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara
A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing. IEICE Trans. Inf. Syst. (9) (2013)
Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura
DART: Dependable VLSI test architecture and its implementation. ITC (2012)
Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara
Low Power BIST for Scan-Shift and Capture Power. Asian Test Symposium (2012)
Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara
A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits. VTS (2012)
Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
On pinpoint capture power management in at-speed scan test generation. ITC (2012)
Senling Wang, Yasuo Sato, Kohei Miyase, Seiji Kajihara
A Scan-Out Power Reduction Method for Multi-cycle BIST. Asian Test Symposium (2012)
Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
A Failure Prediction Strategy for Transistor Aging. IEEE Trans. Very Large Scale Integr. Syst. 20 (11) (2012)
Yukiya Miura, Yasuo Sato, Yousuke Miyake, Seiji Kajihara
On-chip temperature and voltage measurement for field testing. ETS (2012)
Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium (2011)
Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich
SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures. ISLPED (2011)
Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang
A novel scan segmentation design method for avoiding shift timing failure in scan testing. ITC (2011)
Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda
Delay Testing: Improving Test Quality and Avoiding Over-testing. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Kohei Miyase, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara
Transition-Time-Relation based capture-safety checking for at-speed scan test generation. DATE (2011)
Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda
Delay Testing: Improving Test Quality and Avoiding Over-testing. Inf. Media Technol. 6 (4) (2011)
Yasuo Sato, Hisato Yamaguchi, Makoto Matsuzono, Seiji Kajihara
Multi-cycle Test with Partial Observation on Scan-Based BIST Structure. Asian Test Symposium (2011)
Xiaoxin Fan, Sudhakar M. Reddy, Senling Wang, Seiji Kajihara, Yasuo Sato
Genetic algorithm based approach for segmented testing. DSN Workshops (2011)
Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara
Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing. IEICE Trans. Inf. Syst. (6) (2011)
Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara
-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing. IEICE Trans. Inf. Syst. (4) (2011)
Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor
Power-aware test generation with guaranteed launch safety for at-speed scan testing. VTS (2011)
Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
A Study of Capture-Safe Test Generation Flow for At-Speed Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2010)
Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen
On Delay Test Quality for Test Cubes. IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura
On estimation of NBTI-Induced delay degradation. ETS (2010)
Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor
High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme. IEICE Trans. Inf. Syst. (1) (2010)
Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
Aging test strategy and adaptive test scheduling for SoC failure prediction. IOLTS (2010)
Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, Masao Aso, Hiroshi Furukawa
CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing. Asian Test Symposium (2009)
Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara
A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. ICCAD (2009)
Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara
A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing. PRDC (2009)
Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen
Diagnosis of Realistic Defects Based on the X-Fault Model. DDECS (2008)
Yuta Yamato, Yusuke Nakamura, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara
-Fault Model for Deep-Submicron LSI Circuits. IEICE Trans. Inf. Syst. (3) (2008)
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. J. Electron. Test. 24 (4) (2008)
Seiji Kajihara, Michiko Inoue
Special Section on Test and Verification of VLSIs. IEICE Trans. Inf. Syst. (3) (2008)
Hiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor
CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing. ATS (2008)
Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, H. Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. ETS (2008)
Kohei Miyase, Kenta Terashima, Xiaoqing Wen, Seiji Kajihara, Sudhakar M. Reddy
On Detection of Bridge Defects with Stuck-at Tests. IEICE Trans. Inf. Syst. (3) (2008)
Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
Estimation of Delay Test Quality and Its Application to Test Generation. Inf. Media Technol. 3 (4) (2008)
Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. ICCAD (2008)
Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
Estimation of Delay Test Quality and Its Application to Test Generation. IPSJ Trans. Syst. LSI Des. Methodol. 1 (2008)
Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang
A novel scheme to reduce power supply noise for high-quality at-speed scan testing. ITC (2007)
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja
Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. DAC (2007)
Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
A Novel ATPG Method for Capture Power Reduction during Scan Testing. IEICE Trans. Inf. Syst. (9) (2007)
Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
Estimation of delay test quality and its application to test generation. ICCAD (2007)
Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara
A Statistical Quality Model for Delay Testing. IEICE Trans. Electron. (3) (2006)
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. ICCD (2006)
Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
-Fault Model. IEICE Trans. Inf. Syst. (11) (2006)
Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu
On Finding Don't Cares in Test Sequences for Sequential Circuits. IEICE Trans. Inf. Syst. (11) (2006)
Seiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
A Framework of High-quality Transition Fault ATPG for Scan Circuits. ITC (2006)
Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
A dynamic test compaction procedure for high-quality path delay testing. ASP-DAC (2006)
Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. VTS (2006)
Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
A New Method for Low-Capture-Power Test Generation for Scan Testing. IEICE Trans. Inf. Syst. (5) (2006)
Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu
Test cost reduction for logic circuits: Reduction of test data volume and test application time. Systems and Computers in Japan 36 (6) (2005)
Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Nozuyama, Seiji Kajihara
Invisible delay quality - SDQM model lights up what could not be seen. ITC (2005)
Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation. ASP-DAC (2005)
Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja
Efficient Test Set Modification for Capture Power Reduction. J. Low Power Electron. 1 (3) (2005)
Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
Path delay test compaction with process variation tolerance. DAC (2005)
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores. VLSI Design (2005)
Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara
Evaluation of the statistical delay quality model. ASP-DAC (2005)
Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
On Low-Capture-Power Test Generation for Scan Testing. VTS (2005)
Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka
On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis. IEICE Trans. Inf. Syst. (7) (2005)
Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies. IEICE Trans. Inf. Syst. (4) (2005)
Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
Low-capture-power test generation for scan-based at-speed testing. ITC (2005)

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Publication Activity (10 Years)

Top Topics

Top Venues

Seiji Kajihara