Kozo Kinoshita

Publication Activity (10 Years)

Years Active: 1970-2013
Publications (10 Years): 0

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Kozo Kinoshita
SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukinori Nakajima, Kozo Kinoshita
Current-based testable design of level shifters in liquid crystal display drivers. ETS (2010)
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. J. Electron. Test. 24 (4) (2008)
Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
A Novel ATPG Method for Capture Power Reduction during Scan Testing. IEICE Trans. Inf. Syst. (9) (2007)
Hideyuki Ichihara, Toshimasa Kuchii, Masaaki Yamadate, Hideaki Sakaguchi, Hiroshi Uemura, Kozo Kinoshita
A statistical error model for image sensors and its testing. Systems and Computers in Japan 38 (11) (2007)
Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
-Fault Model. IEICE Trans. Inf. Syst. (11) (2006)
Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. VTS (2006)
Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
A New Method for Low-Capture-Power Test Generation for Scan Testing. IEICE Trans. Inf. Syst. (5) (2006)
Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
On Low-Capture-Power Test Generation for Scan Testing. VTS (2005)
Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies. IEICE Trans. Inf. Syst. (4) (2005)
Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
Low-capture-power test generation for scan-based at-speed testing. ITC (2005)
Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees. J. Electron. Test. 21 (6) (2005)
Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
Fault Diagnosis of Physical Defects Using Unknown Behavior Model. J. Comput. Sci. Technol. 20 (2) (2005)
Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
On per-test fault diagnosis using the X-fault model. ICCAD (2004)
Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure. DELTA (2004)
Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa
Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs. VLSI Design (2003)
Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
Fault Diagnosis for Physical Defects of Unknown Behaviors. Asian Test Symposium (2003)
Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita
A BIST Circuit for IDDQ Tests. Asian Test Symposium (2003)
Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
Reducing Scan Shifts Using Folding Scan Trees. Asian Test Symposium (2003)
Kozo Kinoshita
Foreword. J. Electron. Test. 18 (1) (2002)
Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita
Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits. Asian Test Symposium (2002)
Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita
Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits. DELTA (2002)
Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita
On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. ITC (2002)
Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita
Built-in Self-Test for crosstalk faults in a digital VLSI. Systems and Computers in Japan 33 (13) (2002)
Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita
Built-in Self-Test for State Faults Induced by Crosstalk in Sequential Circuits. Asian Test Symposium (2001)
Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita
IDDQ Sensing Technique for High Speed IDDQ Testing. Asian Test Symposium (2001)
Arabi Keshk, Yukiya Miura, Kozo Kinoshita
Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits. Asian Test Symposium (2000)
Toshiyuki Maeda, Kozo Kinoshita
test compaction for internal and external bridging faults. Asian Test Symposium (2000)
Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita
Static test compaction for IDDQ testing of bridging faults in sequential circuits. Systems and Computers in Japan 31 (11) (2000)
Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. J. Electron. Test. 16 (5) (2000)
Toshiyuki Maeda, Kozo Kinoshita
Precise test generation for resistive bridging faults of CMOS combinational circuits. ITC (2000)
Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita
Test sequence compaction for sequential circuits with reset states. Asian Test Symposium (2000)
Yann Antonioli, Tsuneo Inufushi, Shigeki Nishikawa, Kozo Kinoshita
A high-speed IDDQ sensor implementation. Asian Test Symposium (2000)
Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
Test Transformation to Improve Compaction by Statistical Encoding. VLSI Design (2000)
Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
Fault models and test generation for IDDQ testing: embedded tutorial. ASP-DAC (2000)
Toshiyuki Maeda, Kozo Kinoshita
Compaction of IDDQ Test Sequence Using Reassignment Method. J. Electron. Test. 16 (3) (2000)
Arabi Keshk, Kozo Kinoshita, Yukiya Miura
Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits. Asian Test Symposium (1999)
Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita
Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. VLSI Design (1999)
Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
On Test Generation with A Limited Number of Tests. Great Lakes Symposium on VLSI (1999)
Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium (1999)
Arabi Keshk, Kozo Kinoshita, Yukiya Miura
IDDQ Current Dependency on Test Vectors and Bridging Resistance. Asian Test Symposium (1999)
Toshiyuki Maeda, Kozo Kinoshita
Compaction of IDDQ test sequence using reassignment method. ETW (1999)
Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium (1999)
Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita
Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. Asian Test Symposium (1998)
Xiaoqing Wen, Tooru Honzawa, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
Design for Diagnosability of CMOS Circuits. Asian Test Symposium (1998)
Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita
An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification. Asian Test Symposium (1998)
Noriyoshi Itazaki, Fumiro Matsuki, Yasuyuki Matsumoto, Kozo Kinoshita
Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA. Asian Test Symposium (1998)
Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita
A High-Speed IDDQ Sensor for Low-Voltage ICs. Asian Test Symposium (1998)
Hiroyuki Yotsuyanagi, Kozo Kinoshita
Undetectable Fault Removal of Sequential Circuits Based on Unreachable States. VTS (1998)
Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
On invariant implication relations for removing partial circuits. Systems and Computers in Japan 28 (7) (1997)
Atsushi Yoshikawa, Seiji Kajihara, Masahiro Numa, Kozo Kinoshita
A diagnosis method for single logic design errors in gate-level combinational circuits. Systems and Computers in Japan 28 (6) (1997)
Yoshinobu Higami, Kozo Kinoshita
Design of partially parallel scan chain. ED&TC (1997)
Hideyuki Ichihara, Kozo Kinoshita
On Acceleration of Logic Circuits Optimization Using Implication Relations. Asian Test Symposium (1997)
Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita
test vector selection for transistor short fault testing. Systems and Computers in Japan 28 (5) (1997)
Noriyoshi Itazaki, Yasutaka Idomoto, Kozo Kinoshita
An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits. Asian Test Symposium (1997)
Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. VLSI Design (1997)
Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
Synthesis of Sequential Circuits by Redundancy Removal and Retiming. J. Electron. Test. 11 (1) (1997)
Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. Asian Test Symposium (1996)
Noriyoshi Itazaki, Yasutaka Idomoto, Kozo Kinoshita
A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits. FTCS (1996)
Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
Resynthesis for sequential circuits designed with a specified initial state. VTS (1995)
Noriyoshi Itazaki, Kozo Kinoshita, Hisao Naitoh
Test pattern generation for crosstalk faults considering the gate delay. Systems and Computers in Japan 26 (7) (1995)
Seiji Kajihara, Rikiya Nishigaya, Tetsuji Sumioka, Kozo Kinoshita
Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis. IEICE Trans. Inf. Syst. (7) (1995)
Xiaoqing Wen, Kozo Kinoshita, Hideo Tamamoto, Hiroshi Yokoyama
Efficient Guided-Probe Fault Location Method for Sequential Circuits. IEICE Trans. Inf. Syst. (2) (1995)
Hiroaki Ueda, Kozo Kinoshita
Low power design and its testability. Asian Test Symposium (1995)
Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement. IEICE Trans. Inf. Syst. (7) (1995)
Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
Partial scan design and test sequence generation based on reduced scan shift method. J. Electron. Test. 7 (1-2) (1995)
Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (12) (1995)
Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
Synthesis for Testability by Sequential Redundancy Removal Using Retiming. FTCS (1995)
Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita
Transistor leakage fault location with ZDDQ measurement. Asian Test Symposium (1995)
Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita
-FR Circuits under Highly Observable Condition. IEICE Trans. Inf. Syst. (7) (1995)
Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
Test sequence compaction by reduced scan shift and retiming. Asian Test Symposium (1995)
Hiroaki Ueda, Kozo Kinoshita
Evaluation of the maximum number of switching gates for CMOS circuits. Systems and Computers in Japan 26 (14) (1995)
Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
On compacting test sets by addition and removal of test vectors. VTS (1994)
Yukiya Miura, Sachio Naito, Kozo Kinoshita
A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit. ISCAS (1994)
Antonio Rubio, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (3) (1994)
Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
Reduced Scan Shift: A New Testing Method for Sequential Circuit. ITC (1994)
Seiji Kajihara, Kozo Kinoshita, Haruko Shiba
Removal of redundancy in combinational circuits under classification of undetectable faults. Systems and Computers in Japan 24 (7) (1993)
Yukiya Miura, Yasushi Wada, Kozo Kinoshita
Design of testing circuit and test generation for built-in current testing. Systems and Computers in Japan 24 (5) (1993)
Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita
Test generation for multiple faults based on parallel vector pair analysis. ICCAD (1993)
Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. DAC (1993)
Seiji Kajihara, Haruko Shiba, Kozo Kinoshita
Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults. FTCS (1992)
Xiaoqing Wen, Kozo Kinoshita
Testable Designs of Sequential Circuits Under Highly Observable Condition. ITC (1992)
Xiaoqing Wen, Kozo Kinoshita
A Testable Design of Logic Circuits under Highly Observable Condition. IEEE Trans. Computers 41 (5) (1992)
Yukiya Miura, Kozo Kinoshita
Circuit Design for Built-in Current Testing. ITC (1992)
Antonio Rubio, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita
An approach to the analysis and test of crosstalk faults in digital VLSI circuits. EURO-DAC (1991)
Seiji Kajihara, Noriyoshi Itazaki, Kozo Kinoshita
Stuck-open faults test generation for cmos combinational circuits. Systems and Computers in Japan 22 (9) (1991)
Xiaoqing Wen, Kozo Kinoshita
Fault detection and diagnosis of k-UCP circuits under totally observable condition. FTCS (1990)
Xiaoqing Wen, Kozo Kinoshita
A testable design of logic circuits under highly observable condition. ITC (1990)
Etienne Sicard, Kozo Kinoshita
On the evaluation of process-fault tolerance ability of CMOS integrated circuits. ITC (1990)
Yuzo Takamatsu, Kozo Kinoshita
Extended selection of switching target faults in CONT algorithm for test generation. J. Electron. Test. 1 (3) (1990)
Noriyoshi Itazaki, Kozo Kinoshita
Test pattern generation for circuits with tri-state modules by Z-algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (12) (1989)
Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita
Row/column pattern sensitive fault detection in RAMs via built-in self-test. FTCS (1989)
Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita
Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability. ITC (1989)
Yuzo Takamatsu, Kozo Kinoshita
CONT: a concurrent test generation system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (9) (1989)
Kewal K. Saluja, Siew H. Sng, Kozo Kinoshita
Built-In Self-Testing RAM: A Practical Alternative. IEEE Des. Test 4 (1) (1987)
Kozo Kinoshita, Kewal K. Saluja
Built-In Testing of Memory Using an On-Chip Compact Testing Scheme. IEEE Trans. Computers 35 (10) (1986)
Noriyoshi Itazaki, Kozo Kinoshita
Test Pattern Generation for Circuits with Three-state Modules by Improved Z-algorithm. ITC (1986)
Kewal K. Saluja, Kozo Kinoshita
Test Pattern Generation for API Faults in RAM. IEEE Trans. Computers 34 (3) (1985)
C. Boswell, Kewal K. Saluja, Kozo Kinoshita
Design of Programmable Logic Arrays for Parallel Testing. Comput. Syst. Sci. Eng. 1 (1) (1985)
Hideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita
A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead. ITC (1985)

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Publication Activity (10 Years)

Top Topics

Top Venues

Kozo Kinoshita