Hiroyuki Yotsuyanagi

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 16

Top Topics

Test Generation

Defect Detection

Detection Method

Null Hypothesis

Top Venues

IEICE Trans. Inf. Syst.

Publications

Shogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume
On Test Pattern Generation Method for an Approximate Multiplier Considering Acceptable Faults. ITC-Asia (2023)
Masao Ohmatsu, Yuto Ohtera, Yuki Ikiri, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Masaki Hashizume
Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators. ATS (2022)
Shyue-Kung Lu, Shu-Chi Yu, Chun-Lung Hsu, Chi-Tien Sun, Masaki Hashizume, Hiroyuki Yotsuyanagi
Fault-Aware Dependability Enhancement Techniques for Flash Memories. IEEE Trans. Very Large Scale Integr. Syst. 28 (3) (2020)
Hanna Soneda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes. 3DIC (2019)
Toshiaki Satoh, Hiroyuki Yotsuyanagi, Masaki Hashizume
On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection. 3DIC (2019)
Shuya Kikuchi, Hiroyuki Yotsuyanagi, Masaki Hashizume
On Delay Measurement Under Delay Variations in Boundary Scan Circuit with Embedded TDC. ITC-Asia (2019)
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume
Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design. ATS (2018)
Fara Ashikin, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Zvi Roth
A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs. IEICE Trans. Inf. Syst. (8) (2018)
Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi, Masaki Hashizume
A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification. IOLTS (2018)
Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type. DFT (2017)
Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume, Shyue-Kung Lu
Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs. ATS (2017)
Shyue-Kung Lu, Shu-Chi Yu, Masaki Hashizume, Hiroyuki Yotsuyanagi
Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories. ATS (2017)
Yuuya Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami, Hiroshi Takahashi
On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects. ISCIT (2017)
Hiroyuki Yotsuyanagi, Kotaro Ise, Masaki Hashizume, Yoshinobu Higami, Hiroshi Takahashi
Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Kouhei Ohtani, Naho Osato, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume. ISCIT (2017)
Widianto, Masaki Hashizume, Shohei Suenaga, Hiroyuki Yotsuyanagi, Akira Ono, Shyue-Kung Lu, Zvi Roth
A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs. IEICE Trans. Inf. Syst. (11) (2016)
Kosuke Nanbara, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit. 3DIC (2015)
Hiroyuki Yotsuyanagi, Akihiro Fujiwara, Masaki Hashizume
On TSV array defect detection method using two ring-oscillators considering signal transitions at adjacent TSVs. 3DIC (2015)
Daisuke Suga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
Electrical interconnect test method of 3D ICs by injected charge volume. 3DIC (2015)
Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
A built-in supply current test circuit for electrical interconnect tests of 3D ICs. 3DIC (2014)
Masaki Hashizume, Tomoaki Konishi, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs. Asian Test Symposium (2013)
Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Kozo Kinoshita
SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Takanobu Nimiya, Masaki Hashizume
On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan. IEICE Trans. Inf. Syst. (9) (2013)
Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi, Yukiya Miura
A supply current testable register string DAC of decoder type. ISCIT (2011)
Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Masaki Hashizume
A built-in test circuit for open defects at interconnects between dies in 3D ICs. 3DIC (2011)
Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Masaki Hashizume
A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing. Asian Test Symposium (2011)
Tomoaki Konishi, Hiroyuki Yotsuyanagi, Masaki Hashizume
Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture. 3DIC (2011)
Masashi Ishikawa, Hiroyuki Yotsuyanagi, Masaki Hashizume
Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code. Asian Test Symposium (2010)
Hiroyuki Yotsuyanagi, Masayuki Yamamoto, Masaki Hashizume
Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops. IEICE Trans. Inf. Syst. (1) (2010)
Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukinori Nakajima, Kozo Kinoshita
Current-based testable design of level shifters in liquid crystal display drivers. ETS (2010)
Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume
A Novel Approach for Improving the Quality of Open Fault Diagnosis. VLSI Design (2009)
Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume
New Class of Tests for Open Faults with Considering Adjacent Lines. Asian Test Symposium (2009)
Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. VLSI Design (2009)
Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. DFT (2007)
Masaki Hashizume, Yutaka Hata, Tomomi Nishida, Hiroyuki Yotsuyanagi, Yukiya Miura
Current Testable Design of Resistor String DACs. ATS (2007)
Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume
Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines. ATS (2007)
Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yukiya Miura
A BIC Sensor Capable of Adjusting IDDQ Limit in Tests. ATS (2006)
Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura
Current Testable Design of Resistor String DACs. DELTA (2006)
Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada
Electric field for detecting open leads in CMOS logic circuits by supply current testing. ISCAS (3) (2005)
Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees. J. Electron. Test. 21 (6) (2005)
Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita, Takeomi Tamesada
I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment. Asian Test Symposium (2004)
Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
Practical Fault Coverage of Supply Current Tests for Bipolar ICs. DELTA (2004)
Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
A test circuit for pin shorts generating oscillation in CMOS logic circuits. Systems and Computers in Japan 35 (13) (2004)
Masaki Hashizume, Tetsuo Akita, Hiroyuki Yotsuyanagi, Takeomi Tamesada
CMOS Open Fault Detection by Appearance Time of Switching Supply Current. DELTA (2004)
Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits. DELTA (2004)
Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure. DELTA (2004)
Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits. IEICE Trans. Inf. Syst. (3) (2004)
Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada
Test Sequence Generation for Test Time Reduction of IDDQ Testing. IEICE Trans. Inf. Syst. (3) (2004)
Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita
A BIST Circuit for IDDQ Tests. Asian Test Symposium (2003)
Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita
Reducing Scan Shifts Using Folding Scan Trees. Asian Test Symposium (2003)
Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada
Test Time Reduction for I DDQ Testing by Arranging Test Vectors. Asian Test Symposium (2002)
Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Takeomi Tamesada
Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits. DELTA (2002)
Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada
Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field. DELTA (2002)
Hiroyuki Yotsuyanagi, Shinsuke Hata, Masaki Hashizume, Takeomi Tamesada
Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States. Asian Test Symposium (2001)
Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada
Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field. DFT (2001)
Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada
CMOS open defect detection by supply current test. DATE (2001)
Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita
IDDQ Sensing Technique for High Speed IDDQ Testing. Asian Test Symposium (2001)
Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada
CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application. Asian Test Symposium (2001)
Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Masashi Takeda
Testability Analysis of IDDQ Testing with Large Threshold Value. DFT (2000)
Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda
High speed IDDQ test and its testability for process variation. Asian Test Symposium (2000)
Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
Identification of Feedback Bridging Faults with Oscillation. Asian Test Symposium (1999)
Hiroyuki Yotsuyanagi, Kozo Kinoshita
Undetectable Fault Removal of Sequential Circuits Based on Unreachable States. VTS (1998)
Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
Synthesis of Sequential Circuits by Redundancy Removal and Retiming. J. Electron. Test. 11 (1) (1997)
Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
Resynthesis for sequential circuits designed with a specified initial state. VTS (1995)
Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement. IEICE Trans. Inf. Syst. (7) (1995)
Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
Synthesis for Testability by Sequential Redundancy Removal Using Retiming. FTCS (1995)