A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing.

Hiroyuki Yotsuyanagi Hiroyuki Makimoto Masaki Hashizume

Published in: Asian Test Symposium (2011)

Keyphrases

phase locked loop
high voltage
circuit design
single phase
data conversion
low voltage
neural network
high speed
power electronics
multipath
control method
software testing
pulse width modulation
object boundaries
delay insensitive