Yukiya Miura

Publication Activity (10 Years)

Years Active: 1987-2024
Publications (10 Years): 12

Top Topics

Constrained Optimization Problems

Differential Evolution

Top Venues

Publications

Yuki Hanawa, Tomohiro Harada, Yukiya Miura
Analysis of the Impact of Prediction Accuracy on Search Performance in Surrogate-assisted Evolutionary Algorithms. CEC (2024)
Hitomi Kano, Tomohiro Harada, Yukiya Miura, Masahiro Kanazaki
Hybrid Rocket Engine Design Using Pairwise Ranking Surrogate-assisted Differential Evolution. GECCO Companion (2023)
Reo Nakaya, Tomohiro Harada, Yukiya Miura, Kiyohiko Hattori, Johei Matsuoka
Emergence of Cooperative Automated Driving Control at Roundabouts Using Deep Reinforcement Learning. SICE (2023)
Takuya Hakoishi, Tomohiro Harada, Yukiya Miura
Improving Data Sampling Efficiency of Sensitivity Analysis Based on Bilevel Multi-objective Evolutionary Algorithm. SCIS/ISIS (2022)
Hitomi Kano, Tomohiro Harada, Yukiya Miura
Differential Evolution Using Surrogate Model Based on Pairwise Ranking Estimation for Constrained Optimization Problems. SCIS/ISIS (2022)
Yukiya Miura, Shingo Tsutsumi
A Method for Measuring Process Variations in the FPGA Chip Considering the Effect of Wire Delay. IOLTS (2021)
Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Yukiya Miura, Smith Lai, Gavin Hung, Harry H. Chen, Haruo Kobayashi, Kazumi Hatayama
Innovative Test Practices in Asia. VTS (2020)
Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yukiya Miura
On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test. IOLTS (2020)
Yukiya Miura, Yuya Kinoshita
Soft Error Tolerance of Power-Supply-Noise Hardened Latches. IOLTS (2020)
Yukiya Miura, Miyuki Inoue, Yuya Kinoshita
Development of FF Circuits for Measures Against Power Supply Noise. IOLTS (2019)
Yukiya Miura, Takuya Yamamoto
Simulation-based analysis of FF behavior in presence of power supply noise. IOLTS (2017)
Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura
Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor. IEEE Trans. Very Large Scale Integr. Syst. 24 (11) (2016)
Yukiya Miura, Tatsunori Ikeda
LSI aging estimation using ring oscillators. ETS (2015)
Seiji Kajihara, Yousuke Miyake, Yasuo Sato, Yukiya Miura
An On-Chip Digital Environment Monitor for Field Test. ATS (2014)
Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura
Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test. ATS (2014)
Yukiya Miura, Yoshihiro Ohkawa
A noise-tolerant master-slave flip-flop. IOLTS (2014)
Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura
DART: Dependable VLSI test architecture and its implementation. ITC (2012)
Yoshihiro Ohkawa, Yukiya Miura
Dual Edge Triggered Flip-Flops for Noise Blocking and Application to Signal Delay Detection. Asian Test Symposium (2012)
Yukiya Miura, Yasuo Sato, Yousuke Miyake, Seiji Kajihara
On-chip temperature and voltage measurement for field testing. ETS (2012)
Yukiya Miura
Dual Edge Triggered Flip-Flops for Noise Aware Design. ETS (2011)
Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi, Yukiya Miura
A supply current testable register string DAC of decoder type. ISCIT (2011)
Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura
On estimation of NBTI-Induced delay degradation. ETS (2010)
Yukiya Miura, Jiro Kato
Zoning Method. J. Electron. Test. 24 (1-3) (2008)
Yukiya Miura, Jiro Kato
Diagnosis of Analog Circuits by Using Multiple Transistors and Data Sampling. DFT (2008)
Yukiya Miura
Ramp Voltage Testing for Detecting Interconnect Open Faults. IEICE Trans. Inf. Syst. (3) (2008)
Yukiya Miura
Dependable clock distribution for crosstalk aware design. ITC (2007)
Masaki Hashizume, Yutaka Hata, Tomomi Nishida, Hiroyuki Yotsuyanagi, Yukiya Miura
Current Testable Design of Resistor String DACs. ATS (2007)
Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yukiya Miura
A BIC Sensor Capable of Adjusting IDDQ Limit in Tests. ATS (2006)
Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura
Current Testable Design of Resistor String DACs. DELTA (2006)
Yukiya Miura, Jiro Kato
Fault Diagnosis of Analog Circuits Based on Adaptive Test and Output Characteristics. DFT (2006)
Yukiya Miura
Detection of Interconnect Open Faults with Unknown Values by Ramp Voltage Application. ATS (2006)
Yukiya Miura
Zoning Method: Case Study. J. Electron. Test. 22 (4-6) (2006)
Yukiya Miura
Characteristics of Fault Diagnosis for Analog Circuits Based on Preset Test. DFT (2005)
Yukiya Miura
Analysis and Testing of Bridging Faults in CMOS Synchronous Sequential Circuits. IEICE Trans. Inf. Syst. (3) (2004)
Yukiya Miura
Fault Diagnosis of Analog Circuits by Operation-Region Model and X-Y Zoning Method. DFT (2004)
Yukiya Miura, Daisuke Kato
Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study of Application and Implementation. DFT (2003)
Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita
A BIST Circuit for IDDQ Tests. Asian Test Symposium (2003)
Yukiya Miura, Shuichi Seno
Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits. J. Electron. Test. 18 (2) (2002)
Yukiya Miura
Proposal of an Operation-Region Model for Analyzing Analog and Mixed-Signal Circuits. LATW (2001)
Yukiya Miura, Shuichi Seno
Internal feedback bridging faults in combinational CMOS circuits: analysis and testing. ETW (2001)
Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita
IDDQ Sensing Technique for High Speed IDDQ Testing. Asian Test Symposium (2001)
Arabi Keshk, Yukiya Miura, Kozo Kinoshita
Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits. Asian Test Symposium (2000)
Yukiya Miura, Hiroshi Yamazaki
A Low-Loss Built-In Current Sensor. J. Electron. Test. 14 (1-2) (1999)
Arabi Keshk, Kozo Kinoshita, Yukiya Miura
Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits. Asian Test Symposium (1999)
Arabi Keshk, Kozo Kinoshita, Yukiya Miura
IDDQ Current Dependency on Test Vectors and Bridging Resistance. Asian Test Symposium (1999)
Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita
A High-Speed IDDQ Sensor for Low-Voltage ICs. Asian Test Symposium (1998)
Yukiya Miura
An IDDQ Sensor Circuit for Low-Voltage ICs. ITC (1997)
Yukiya Miura
Real-Time Current Testing for A/D Converters. IEEE Des. Test Comput. 13 (2) (1996)
Yukiya Miura, Sachio Naito
A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs. IEICE Trans. Inf. Syst. (7) (1995)
Yukiya Miura
A Comparative Analysis of Input Stimuli for Testing Mixed-Signal LSIs Based on Curent Testing. ITC (1995)
Yukiya Miura, Sachio Naito, Kozo Kinoshita
A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit. ISCAS (1994)
Yukiya Miura, Yasushi Wada, Kozo Kinoshita
Design of testing circuit and test generation for built-in current testing. Systems and Computers in Japan 24 (5) (1993)
Yukiya Miura, Kozo Kinoshita
Circuit Design for Built-in Current Testing. ITC (1992)
Yukiya Miura, Hideo Tamamoto, Yuichi Narita
Built - in concurrent testing for semiconductor random access memories by concurrently testing cells on a word-line. Systems and Computers in Japan 19 (6) (1988)
Yukiya Miura, Hideo Tamamoto, Yuichi Narita
A built-in test for functional testing in semiconductor random access memory. Systems and Computers in Japan 18 (9) (1987)