Sachio Naito

Publication Activity (10 Years)

Years Active: 1969-1995
Publications (10 Years): 0

Publications

Yukiya Miura, Sachio Naito
A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs. IEICE Trans. Inf. Syst. (7) (1995)
Yukiya Miura, Sachio Naito, Kozo Kinoshita
A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit. ISCAS (1994)
Masataka Kawanaka, Masahiro Tsunoyama, Sachio Naito
A fault-tolerant parallel processor modeled by a two-dimensional linear cellular automaton. Systems and Computers in Japan 25 (6) (1994)
Masahiro Tsunoyama, Sachio Naito
A Fault-Tolerant FFT Processor. FTCS (1991)
Masahiro Tsunoyama, Sachio Naito
A fault-tolerant parallel processor modeled by a linear cellular automaton. FTCS (1988)
Sachio Naito, Osamu Fujinawa
Polytonic fault-free combinational circuits for alternate-data-retry. Systems and Computers in Japan 18 (8) (1987)
Kenji Ohmori, Sachio Naito, T. Nanya, Koji Nezu
An application of cellular logic for high speed decoding of minimum-redundancy codes. AFIPS Fall Joint Computing Conference (1) (1972)
Koji Nezu, Sachio Naito
Economical display generation of a large character set. AFIPS Fall Joint Computing Conference (1969)