An application of cellular logic for high speed decoding of minimum-redundancy codes.
Kenji OhmoriSachio NaitoT. NanyaKoji NezuPublished in: AFIPS Fall Joint Computing Conference (1) (1972)
Keyphrases
- high speed
- minimum redundancy
- decoding algorithm
- error control
- ldpc codes
- logical operations
- error correcting
- low power
- parity check
- reed solomon
- error correction
- low density parity check
- modal logic
- decoding complexity
- joint source channel
- cellular automata
- frame rate
- classical logic
- logic programming
- feature selection
- reed solomon codes
- multi valued
- turbo codes
- error correcting codes
- asynchronous circuits
- decoding process
- low cost
- rate allocation
- error detection