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Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits.
Arabi Keshk
Yukiya Miura
Kozo Kinoshita
Published in:
Asian Test Symposium (2000)
Keyphrases
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transmission line
low voltage
circuit design
high speed
analog vlsi
delay insensitive
power supply
random access memory
vlsi circuits
cmos technology
low power
chip design
fault detection
fault diagnosis
power system
parallel processing