Takeomi Tamesada

Publication Activity (10 Years)

Years Active: 1980-2006
Publications (10 Years): 0

Publications

Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura
Current Testable Design of Resistor String DACs. DELTA (2006)
Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada
Electric field for detecting open leads in CMOS logic circuits by supply current testing. ISCAS (3) (2005)
Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita, Takeomi Tamesada
I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment. Asian Test Symposium (2004)
Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
Practical Fault Coverage of Supply Current Tests for Bipolar ICs. DELTA (2004)
Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
A test circuit for pin shorts generating oscillation in CMOS logic circuits. Systems and Computers in Japan 35 (13) (2004)
Masaki Hashizume, Tetsuo Akita, Hiroyuki Yotsuyanagi, Takeomi Tamesada
CMOS Open Fault Detection by Appearance Time of Switching Supply Current. DELTA (2004)
Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits. DELTA (2004)
Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits. IEICE Trans. Inf. Syst. (3) (2004)
Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada
Test Sequence Generation for Test Time Reduction of IDDQ Testing. IEICE Trans. Inf. Syst. (3) (2004)
Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita
A BIST Circuit for IDDQ Tests. Asian Test Symposium (2003)
Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada
Test Time Reduction for I DDQ Testing by Arranging Test Vectors. Asian Test Symposium (2002)
Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Takeomi Tamesada
Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits. DELTA (2002)
Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada
Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field. DELTA (2002)
Hiroyuki Yotsuyanagi, Shinsuke Hata, Masaki Hashizume, Takeomi Tamesada
Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States. Asian Test Symposium (2001)
Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada
Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field. DFT (2001)
Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada
CMOS open defect detection by supply current test. DATE (2001)
Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada
CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application. Asian Test Symposium (2001)
Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Masashi Takeda
Testability Analysis of IDDQ Testing with Large Threshold Value. DFT (2000)
Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda
High speed IDDQ test and its testability for process variation. Asian Test Symposium (2000)
Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada
Identification of Feedback Bridging Faults with Oscillation. Asian Test Symposium (1999)
Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita
A High-Speed IDDQ Sensor for Low-Voltage ICs. Asian Test Symposium (1998)
Masaki Hashizume, Toshimasa Kuchii, Takeomi Tamesada
Supply Current Test for Unit-to-unit Variations of Electrical Characteristics in Gates. Asian Test Symposium (1997)
Toshimasa Kuchii, Masaki Hashizume, Takeomi Tamesada
Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits. Asian Test Symposium (1996)
Masaki Hashizume, Takeomi Tamesada, Akio Sakamoto
A Maximum Clique Derivation Algorithm for Simplification of Incompletely Specified Machines. ISCAS (1994)
Masaki Hashizume, Takeomi Tamesada, Koji Nii
A parameter adjustment method for analog circuits based on convex fuzzy decision using constraints of satisfactory level. ICCD (1990)
Takeomi Tamesada
High-speed multioperand addition and subtraction using a p-ary representation with necessary and minimum redundancy. Systems and Computers in Japan 20 (4) (1989)
Masaki Hashizume, Hirosuke Yamamoto, Takeomi Tamesada, Toshiaki Hanibuti
Evaluation of a retrieval system using content addressable memory. Systems and Computers in Japan 20 (7) (1989)
Masaki Hashizume, Takeomi Tamesada, Kazuhiro Yamada, Masaaki Kawakami
Fault Detection of Combinational Circuits Based on Supply Current. ITC (1988)
Takeomi Tamesada
High-speed addition and subtraction using a minimum redundant p-ary representation. Systems and Computers in Japan 19 (11) (1988)
Takeomi Tamesada
Sequential Machines Having Quasi-Stable States. IEEE Trans. Computers 29 (5) (1980)