Yasuo Sato

Publication Activity (10 Years)

Years Active: 1983-2020
Publications (10 Years): 13

Top Topics

Memory Hierarchy

Power Reduction

Top Venues

IEICE Trans. Inf. Syst.

Publications

Gian Mayuga, Yasuo Sato, Michiko Inoue
Highly Reliable Memory Architecture Using Adaptive Combination of Proactive Aging-Aware In-Field Self-Repair and ECC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (8) (2020)
Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen
A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips. IEEE Trans. Emerg. Top. Comput. 8 (3) (2020)
Yousuke Miyake, Yasuo Sato, Seiji Kajihara
On-Chip Delay Measurement for In-Field Test of FPGAs. PRDC (2019)
Yousuke Miyake, Yasuo Sato, Seiji Kajihara
A Selection Method of Ring Oscillators for An On-Chip Digital Temperature And Voltage Sensor. ITC-Asia (2019)
Shigeyuki Oshima, Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara
On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST. ATS (2018)
Takeru Nishimi, Yasuo Sato, Seiji Kajihara, Yoshiyuki Nakamura
Good Die Prediction Modelling from Limited Test Items. ITC-Asia (2018)
Yousuke Miyake, Yasuo Sato, Seiji Kajihara
On the effects of real time and contiguous measurement with a digital temperature and voltage sensor. ITC-Asia (2017)
Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen
A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST. ATS (2016)
Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue
Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair. IEICE Trans. Inf. Syst. (10) (2016)
Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue
Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC. ETS (2016)
Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura
Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor. IEEE Trans. Very Large Scale Integr. Syst. 24 (11) (2016)
Senling Wang, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi
Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip. J. Low Power Electron. 11 (4) (2015)
Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato
An ECC-based memory architecture with online self-repair capabilities for reliability enhancement. ETS (2015)
Seiji Kajihara, Yousuke Miyake, Yasuo Sato, Yukiya Miura
An On-Chip Digital Environment Monitor for Field Test. ATS (2014)
Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura
Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test. ATS (2014)
Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. IEICE Trans. Inf. Syst. (10) (2014)
Yasuo Sato, Masafumi Monden, Yousuke Miyake, Seiji Kajihara
Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA. PRDC (2014)
Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. Asian Test Symposium (2013)
Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase
Scan-Out Power Reduction for Logic BIST. IEICE Trans. Inf. Syst. (9) (2013)
Yasuo Sato, Seiji Kajihara
A Stochastic Model for NBTI-Induced LSI Degradation in Field. Asian Test Symposium (2013)
Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura
DART: Dependable VLSI test architecture and its implementation. ITC (2012)
Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara
Low Power BIST for Scan-Shift and Capture Power. Asian Test Symposium (2012)
Senling Wang, Yasuo Sato, Kohei Miyase, Seiji Kajihara
A Scan-Out Power Reduction Method for Multi-cycle BIST. Asian Test Symposium (2012)
Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
A Failure Prediction Strategy for Transistor Aging. IEEE Trans. Very Large Scale Integr. Syst. 20 (11) (2012)
Yukiya Miura, Yasuo Sato, Yousuke Miyake, Seiji Kajihara
On-chip temperature and voltage measurement for field testing. ETS (2012)
Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara
Temperature-Variation-Aware Test Pattern Optimization. ETS (2011)
Yasuo Sato
Special session: Multifaceted approaches for field reliability. VTS (2011)
Yasuo Sato, Hisato Yamaguchi, Makoto Matsuzono, Seiji Kajihara
Multi-cycle Test with Partial Observation on Scan-Based BIST Structure. Asian Test Symposium (2011)
Xiaoxin Fan, Sudhakar M. Reddy, Senling Wang, Seiji Kajihara, Yasuo Sato
Genetic algorithm based approach for segmented testing. DSN Workshops (2011)
Yasuo Sato
Circuit Failure Prediction by Field Test - A New Task of Testing. DFT (2010)
Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara
Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. VTS (2010)
Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen
On Delay Test Quality for Test Cubes. IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura
On estimation of NBTI-Induced delay degradation. ETS (2010)
Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
Aging test strategy and adaptive test scheduling for SoC failure prediction. IOLTS (2010)
Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato
Post-BIST Fault Diagnosis for Multiple Faults. IEICE Trans. Inf. Syst. (3) (2008)
Yasuharu Kohiyama, C. P. Ravikumar, Yasuo Sato, Laung-Terng Wang, Yervant Zorian
Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides. ATS (2007)
Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara
A Statistical Quality Model for Delay Testing. IEICE Trans. Electron. (3) (2006)
Seiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
A Framework of High-quality Transition Fault ATPG for Scan Circuits. ITC (2006)
Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
A dynamic test compaction procedure for high-quality path delay testing. ASP-DAC (2006)
Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato
Effective Post-BIST Fault Diagnosis for Multiple Faults. DFT (2006)
Yasuo Sato, Kazushi Sugiura, Reisuke Shimoda, Yutaka Yoshizawa, Kenji Norimatsu, Masaru Sanada
Defect Diagnosis - Reasoning Methodology. ATS (2006)
Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Noduyama, Yasuo Sato
Recognition of Sensitized Longest Paths in Transition Delay Test. ITC (2006)
Anis Uzzaman, Mick Tegethoff, Bibo Li, Kevin Mc Cauley, Shuji Hamada, Yasuo Sato
Not all Delay Tests Are the Same - SDQL Model Shows True-Time. ATS (2006)
Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Takeo Kobayashi, Janusz Rajski, Bruce Swanson, Darryl Walters, Yasuo Sato, Toshiharu Asaka, Takashi Aikyo
At-Speed Testing with Timing Exceptions and Constraints-Case Studies. ATS (2006)
Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. ATS (2006)
Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Nozuyama, Seiji Kajihara
Invisible delay quality - SDQM model lights up what could not be seen. ITC (2005)
Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
Path delay test compaction with process variation tolerance. DAC (2005)
Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara
Evaluation of the statistical delay quality model. ASP-DAC (2005)
Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Kazuhiko Iwasaki
Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration. IEICE Trans. Inf. Syst. (9) (2004)
Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Kazumi Hatayama, Kazuyuki Nomoto
DFT Timing Design Methodology for Logic BIST. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Masatoshi Kawashima, Kazumi Hatayama, Kazuyuki Nomoto
DFT timing design methodology for at-speed BIST. ASP-DAC (2003)
Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo
Application of High-Quality Built-In Test to Industrial Designs. ITC (2002)
Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura
A Persistent Diagnostic Technique for Unstable Defects. ITC (2002)
Kazumi Hatayama, Michinobu Nakao, Yasuo Sato
At-Speed Built-in Test for Logic Circuits with Multiple Clocks. Asian Test Symposium (2002)
Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Yasuo Sato
An Approach to Improve the Resolution of Defect-Based Diagnosis. Asian Test Symposium (2001)
Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Toyohito Ikeya, Masatoshi Kawashima
A Practical Logic BIST for ASIC Designs. Asian Test Symposium (2001)
Yasuo Sato, Masaki Kohno, Toshio Ikeda, Iwao Yamazaki, Masato Hamamoto
An evaluation of defect-oriented test: WELL-controlled low voltage test. ITC (2001)
Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo
Test Generation for Multiple-Threshold Gate-Delay Fault Model. Asian Test Symposium (2001)
Yasuo Sato, Toyohito Ikeya, Michinobu Nakao, Takaharu Nagumo
A BIST approach for very deep sub-micron (VDSM) defects. ITC (2000)
Yasuo Sato, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
A Snapshot Algorithm for Distributed Mobile Systems. ICDCS (1996)
Yasushi Ogawa, Tsutomu Itoh, Yoshio Miki, Tatsuki Ishii, Yasuo Sato, Reiji Toyoshima
Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design. DAC (1991)
Koji Tajima, Mitsuo Komura, Yasuo Sato
Connected word recognition by overlap and split of reference patterns and its performance evaluation tests. ICASSP (1986)
Hiroya Fujisaki, Keikichi Hirose, Tomohiro Inoue, Yasuo Sato
Automatic recognition of spoken words from a large vocabulary using syllable templates. ICASSP (1984)
Hynek Hermansky, Hiroya Fujisaki, Yasuo Sato
Spectral envelope sampling and interpolation in linear predictive analysis of speech. ICASSP (1984)
Hynek Hermansky, Hiroya Fujisaki, Yasuo Sato
Analysis and synthesis of speech based on spectral transform linear predictive method. ICASSP (1983)