Anis Uzzaman

Publication Activity (10 Years)

Years Active: 2005-2010
Publications (10 Years): 0

Publications

Anis Uzzaman, Brion L. Keller, Brian Foutz, Sandeep Bhatia, Thomas Bartenstein, Masayuki Arai, Kazuhiko Iwasaki
Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression. IEICE Trans. Inf. Syst. (1) (2010)
Brion L. Keller, Dale Meehl, Anis Uzzaman, Richard Billings
A Partially-Exhaustive Gate Transition Fault Model. Asian Test Symposium (2009)
Anis Uzzaman
Is Low Power Testing Necessary? What does the Test Industry Truly Need?. Asian Test Symposium (2009)
Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman
Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. Asian Test Symposium (2009)
Anis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai
Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test. J. Low Power Electron. 5 (4) (2009)
Anis Uzzaman
How To Increase the Effectiveness of Yield Diagnostics-Is DFM the Answer to This? ATS (2008)
Brion L. Keller, Sandeep Bhatia, Thomas Bartenstein, Brian Foutz, Anis Uzzaman
Optimizing Test Data Volume Using Hybrid Compression. ATS (2008)
Brion L. Keller, Anis Uzzaman, Bibo Li, Thomas J. Snethen
Using Programmable On-Product Clock Generation (OPCG) for Delay Test. ATS (2007)
Anis Uzzaman, Fidel Muradali, Takashi Aikyo, Robert C. Aitken, Tom Jackson, Rajesh Galivanche, Takeshi Onodera
Test Roles in Diagnosis and Silicon Debug. ATS (2007)
Brion L. Keller, Tom Jackson, Anis Uzzaman
A Review of Power Strategies for DFT and ATPG. ATS (2007)
Anis Uzzaman, Bibo Li, Thomas J. Snethen, Brion L. Keller, Gary Grise
Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation. ITC (2007)
Sanae Seike, Ken Namura, Yukio Ohya, Anis Uzzaman, Shinichi Arima, Dale Meehl, Vivek Chickermane, Azumi Kobayashi, Satoshi Tanaka, Hiroyuki Adachi
Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis. ATS (2006)
Anis Uzzaman, Mick Tegethoff, Bibo Li, Kevin Mc Cauley, Shuji Hamada, Yasuo Sato
Not all Delay Tests Are the Same - SDQL Model Shows True-Time. ATS (2006)
Anis Uzzaman, Brion L. Keller, Vivek Chickermane
A Scalable Architecture for On-Chip Compression: Options and Trade-Offs. ATS (2006)
Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman
Practical Aspects of Delay Testing for Nanometer Chips. Asian Test Symposium (2005)
Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi
Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. Asian Test Symposium (2005)