Rajesh Galivanche

Publication Activity (10 Years)

Years Active: 1989-2017
Publications (10 Years): 3

Top Topics

Predicate Logic

Built In Self Test

Error Detection

Power Consumption

Top Venues

IEEE Trans. Computers

J. Electron. Test.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Martin Omaña, Marco Padovani, Kreshnik Veliu, Cecilia Metra, Juergen Alt, Rajesh Galivanche
New Approaches for Power Binning of High Performance Microprocessors. IEEE Trans. Computers 66 (7) (2017)
Martin Omaña, Daniele Rossi, Filippo Fuzzi, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Martin Omaña, Daniele Rossi, Edda Beniamino, Cecilia Metra, Chandrasekharan Tirumurti, Rajesh Galivanche
Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST. IEEE Trans. Computers 65 (8) (2016)
Martin Omaña, Daniele Rossi, Edda Beniamino, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche
Power droop reduction during Launch-On-Shift scan-based logic BIST. DFT (2014)
Daniele Rossi, Martin Omaña, G. Garrammone, Cecilia Metra, Abhijit Jas, Rajesh Galivanche
Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder. J. Electron. Test. 29 (3) (2013)
Michail Maniatakos, Chandrasekharan Tirumurti, Rajesh Galivanche, Yiorgos Makris
Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors. IEEE Trans. Computers 61 (10) (2012)
Cecilia Metra, Rajesh Galivanche
Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems. IEEE Trans. Computers 60 (9) (2011)
Suriyaprakash Natarajan, Arun Krishnamachary, Eli Chiprout, Rajesh Galivanche
Path coverage based functional test generation for processor marginality validation. ITC (2010)
Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor
Bridging pre-silicon verification and post-silicon validation. DAC (2010)
Daniele Rossi, Martin Omaña, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. Conf. Computing Frontiers (2010)
Gadi Singer, Rajesh Galivanche, Srinivas Patil, Mike Tripp
The Challenges of Nanotechnology and Gigacomplexity. IEEE Des. Test Comput. 26 (1) (2009)
Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche
Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic. ETS (2008)
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche
A low-cost concurrent error detection technique for processor control logic. DATE (2008)
Rajesh Galivanche, Rohit Kapur, Antonio Rubio
Testing in the year 2020. DATE (2007)
Anis Uzzaman, Fidel Muradali, Takashi Aikyo, Robert C. Aitken, Tom Jackson, Rajesh Galivanche, Takeshi Onodera
Test Roles in Diagnosis and Silicon Debug. ATS (2007)
Rajesh Galivanche, Bob Gottlieb
Session Abstract. VTS (2006)
Rajesh Galivanche
Is the concern for soft-error overblown? ITC (2005)
Sandip Kundu, T. M. Mak, Rajesh Galivanche
Trends in manufacturing test methods and their implications. ITC (2004)
Bill Grundmann, Rajesh Galivanche, Sandip Kundu
Circuit and Platform Design Challenges in Technologies beyond 90nm. DATE (2003)
Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche
Test Challenges in Nanometer Technologies. J. Electron. Test. 17 (3-4) (2001)
Sandip Kundu, Sanjay Sengupta, Rajesh Galivanche
Test challenges in nanometer technologies. ETW (2000)
Dick L. Liu, Rajesh Galivanche, Charlie C. Hsu
An automatic test pattern generation program for large ASICs. ICCD (1989)