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Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST.

Martin OmañaDaniele RossiFilippo FuzziCecilia MetraChandra TirumurtiRajesh Galivanche
Published in: IEEE Trans. Very Large Scale Integr. Syst. (2017)
Keyphrases
  • built in self test
  • power consumption
  • modal logic
  • chip design
  • real time
  • logic programming
  • predicate logic
  • automated reasoning
  • reduction method
  • set theory
  • data mining
  • expert systems
  • multi valued
  • defeasible logic