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Power droop reduction during Launch-On-Shift scan-based logic BIST.

Martin OmañaDaniele RossiEdda BeniaminoCecilia MetraChandra TirumurtiRajesh Galivanche
Published in: DFT (2014)
Keyphrases
  • built in self test
  • logic programming
  • power consumption
  • modal logic
  • reduction method
  • predicate logic
  • power distribution
  • chip design
  • data sets
  • knowledge base
  • website
  • life cycle
  • classical logic
  • single scan