Miron Abramovici

Publication Activity (10 Years)

Years Active: 1977-2017
Publications (10 Years): 1

Top Topics

Keynote Address

Optimal Solution

Top Venues

Publications

Sandeep Gupta, Miron Abramovici, Magdy Abadir, Sridhar Narayanan
Keynote address tribute to Professor Mel Breuer: Contributions to CAD and Test. VTS (2017)
Swarup Bhunia, Miron Abramovici, Dakshi Agrawal, Paul Bradley, Michael S. Hsiao, Jim Plusquellic, Mohammad Tehranipoor
Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution. IEEE Des. Test 30 (3) (2013)
Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor
Bridging pre-silicon verification and post-silicon validation. DAC (2010)
Miron Abramovici, Al Crouch
We need more standards like IEEE 1500. IEEE Des. Test Comput. 26 (1) (2009)
Miron Abramovici, Paul Bradley
Integrated circuit security: new threats and solutions. CSIIRW (2009)
Miron Abramovici
In-system silicon validation using a reconfigurable platform. HLDVT (2008)
Miron Abramovici
In-System Silicon Validation and Debug. IEEE Des. Test Comput. 25 (3) (2008)
Miron Abramovici, Kees Goossens, Bart Vermeulen, Jack Greenbaum, Neal Stollon, Adam Donlin
You can catch more bugs with transaction level honey. CODES+ISSS (2008)
John M. Emmert, Charles E. Stroud, Miron Abramovici
Online Fault Tolerance for FPGA Logic Blocks. IEEE Trans. Very Large Scale Integr. Syst. 15 (2) (2007)
Miron Abramovici, Paul Bradley, Kumar N. Dwarakanath, Peter Levin, Gérard Memmi, Dave Miller
A reconfigurable design-for-debug infrastructure for SoCs. DAC (2006)
Rodrigo Picos, Oscar Calvo, Miquel Roca, Eugenio García-Moreno, Miron Abramovici
Improved Fault Detection Using a Charge Monitor. LATW (2006)
Xiaoming Yu, Miron Abramovici
Sequential circuit ATPG using combinational algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (8) (2005)
Miron Abramovici, Charles E. Stroud, John M. Emmert
Online BIST and BIST-based diagnosis of FPGA logic blocks. IEEE Trans. Very Large Scale Integr. Syst. 12 (12) (2004)
Miron Abramovici, Charles E. Stroud
BIST-Based Delay-Fault Testing in FPGAs. J. Electron. Test. 19 (5) (2003)
Charles E. Stroud, Jeremy Nall, Matthew Lashinsky, Miron Abramovici
BIST-Based Diagnosis of FPGA Interconnect. ITC (2002)
Miron Abramovici, Xiaoming Yu, Elizabeth M. Rudnick
Low-cost sequential ATPG with clock-control DFT. DAC (2002)
Miron Abramovici, Charles E. Stroud
BIST-Based Delay-Fault Testing in FPGAs. IOLTW (2002)
Miron Abramovici, Charles E. Stroud, Marty Emmert
Using embedded FPGAs for SoC yield improvement. DAC (2002)
Miron Abramovici
Design for Testability Techniques: A Comparative Analysis. LATW (2001)
Miron Abramovici, Charles E. Stroud
BIST-based test and diagnosis of FPGA logic blocks. IEEE Trans. Very Large Scale Integr. Syst. 9 (1) (2001)
John M. Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici
On-Line Fault Tolerance for FPGA Interconnect with Roving STARs. DFT (2001)
Miron Abramovici, Charles E. Stroud, Matthew Lashinsky, Jeremy Nall, John M. Emmert
On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs. IOLTW (2001)
Jongshin Shin, Xiaoming Yu, Elizabeth M. Rudnick, Miron Abramovici
At-speed logic BIST using a frozen clock testing strategy. ITC (2001)
José T. de Sousa, João P. Marques Silva, Miron Abramovici
A Configurable Hardware/Software Approach to SAT Solving. FCCM (2001)
Miron Abramovici, John M. Emmert, Charles E. Stroud
Roving Stars: An Integrated Approach To On-Line Testing, Diagnosis, And Fault Tolerance For Fpgas In Adaptive Computing Systems. Evolvable Hardware (2001)
Miron Abramovici, Xiaoming Yu, Elizabeth M. Rudnick
Sequential ATPG Using Combinational Algorithms. LATW (2001)
David E. Long, Mahesh A. Iyer, Miron Abramovici
FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults. ACM Trans. Design Autom. Electr. Syst. 5 (3) (2000)
Elizabeth M. Rudnick, Miron Abramovici
Compact Test Generation Using a Frozen Clock Testing Strategy. J. Inf. Sci. Eng. 16 (5) (2000)
Qiang Peng, Miron Abramovici, Jacob Savir
MUST: multiple-stem analysis for identifying sequentially untestable faults. ITC (2000)
John M. Emmert, Charles E. Stroud, Brandon Skaggs, Miron Abramovici
Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration. FCCM (2000)
Miron Abramovici, José T. de Sousa
A SAT Solver Using Reconfigurable Hardware and Virtual Logic. J. Autom. Reason. 24 (1/2) (2000)
John M. Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron Abramovici
Performance Penalty for Fault Tolerance in Roving STARs. FPL (2000)
Miron Abramovici, Charles E. Stroud
DIST-based detection and diagnosis of multiple faults in FPGAs. ITC (2000)
Miron Abramovici, Charles E. Stroud, Brandon Skaggs, John M. Emmert
Improving On-Line BIST-Based Diagnosis for Roving STARs. IOLTW (2000)
Miron Abramovici, José T. de Sousa
A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware. FCCM (1999)
Miron Abramovici, José T. de Sousa, Daniel G. Saab
A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. DAC (1999)
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rudnick, Miron Abramovici
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy. DATE (1999)
Miron Abramovici, Charles E. Stroud, Carter Hamilton, Sajitha Wijesuriya, Vinay Verma
Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications. ITC (1999)
Charles E. Stroud, Sajitha Wijesuriya, Carter Hamilton, Miron Abramovici
Built-in self-test of FPGA interconnect. ITC (1998)
Miron Abramovici, Prem R. Menon
Fault simulation on reconfigurable hardware. FCCM (1997)
Charles E. Stroud, Eric Lee, Miron Abramovici
BIST-Based Diagnostics of FPGA Logic Blocks. ITC (1997)
Miron Abramovici, Daniel G. Saab
Satisfiability on reconfigurable hardware. FPL (1997)
Mahesh A. Iyer, David E. Long, Miron Abramovici
Surprises in Sequential Redundancy Identification. ED&TC (1996)
Charles E. Stroud, Eric Lee, Srinivasa Konala, Miron Abramovici
Using ILA Testing for BIST in FPGAs. ITC (1996)
Krishna B. Rajan, David E. Long, Miron Abramovici
Increasing testability by clock transformation (getting rid of those darn states). VTS (1996)
Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). VTS (1996)
Mahesh A. Iyer, David E. Long, Miron Abramovici
Identifying Sequential Redundancies Without Search. DAC (1996)
Charles E. Stroud, Ping Chen, Srinivasa Konala, Miron Abramovici
Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks. FPGA (1996)
Mahesh A. Iyer, Miron Abramovici
FIRE: a fault-independent combinational redundancy identification algorithm. IEEE Trans. Very Large Scale Integr. Syst. 4 (2) (1996)
David E. Long, Mahesh A. Iyer, Miron Abramovici
Identifying sequentially untestable faults using illegal states. VTS (1995)
Prashant S. Parikh, Miron Abramovici
On Combining Design for Testability Techniques. ITC (1995)
Prashant S. Parikh, Miron Abramovici
Testability-based partial scan analysis. J. Electron. Test. 7 (1-2) (1995)
Mahesh A. Iyer, Miron Abramovici
Sequentially Untestable Faults Identified Without Search ("Simple Implications Beat Exhaustive Search!"). ITC (1994)
Mahesh A. Iyer, Miron Abramovici
Low-Cost Redundancy Identification for Combinatorial Circuits. VLSI Design (1994)
Miron Abramovici, Prashant S. Parikh, Ben Mathew, Daniel G. Saab
On Selecting Flip-Flops for Partial Reset. ITC (1993)
Miron Abramovici
DOs and DON'Ts in Computing Fault Coverage. ITC (1993)
Prashant S. Parikh, Miron Abramovici
A Cost-Based Approach to Partial Scan. DAC (1993)
Miron Abramovici, Mahesh A. Iyer
One-Pass Redundancy Identification and Removal. ITC (1992)
Miron Abramovici, Prashant S. Parikh
Warning: 100% Fault Coverage May Be Misleading!! ITC (1992)
Miron Abramovici, Krishna B. Rajan, David T. Miller
Freeze!: A New Approach for Testing Sequential Circuits. DAC (1992)
Miron Abramovici, David T. Miller, Rabindra K. Roy
Dynamic redundancy identification in automatic test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (3) (1992)
Premachandran R. Menon, Ytzhak H. Levendel, Miron Abramovici
SCRIPT: a critical path tracing algorithm for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (6) (1991)
Miron Abramovici, James J. Kulikowski, Rabindra K. Roy
The Best Flip-Flops to Scan. ITC (1991)
Miron Abramovici, David T. Miller, R. Henning
Global cost functions for test generation. ITC (1990)
Miron Abramovici, David T. Miller, Rabindra K. Roy
Dynamic redundancy identification in automatic test generation. ICCAD (1989)
Miron Abramovici, James J. Kulikowski, David T. Miller, Prem R. Menon
System-level design verification in the AT&T Computer Division: tools. ICCD (1989)
Miron Abramovici, J. W. Bierbauer, R. H. Hellman, C. L. Hong, David T. Miller, R. G. Taylor
System-level design verification in the AT&T computer division: overview and strategy. ICCD (1989)
Miron Abramovici, Balaji Krishnamurthy, Rob Mathews, Bill Rogers, Michael Schulz, Sharad Seth, John A. Waicukauski
What is the Path to Fast Fault Simulation? ITC (1988)
Prem R. Menon, Ytzhak H. Levendel, Miron Abramovici
Critical path tracing in sequential circuits. ICCAD (1988)
Miron Abramovici, Prem R. Menon, David T. Miller
Checkpoint Faults are not Sufficient Target Faults for Test Generation. IEEE Trans. Computers 35 (8) (1986)
Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller
SMART and FAST: Test Generation for VLSI Scan-Design Circuits. IEEE Des. Test 3 (4) (1986)
Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller
Test Generation In Lamp2: Concepts and Algorithms. ITC (1985)
Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller
Test Generation In Lamp2: System Overview. ITC (1985)
Miron Abramovici, Prem R. Menon
A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. IEEE Trans. Computers 34 (7) (1985)
Miron Abramovici
Low-Cost Fault Simulation: Why, When and How. ITC (1985)
Miron Abramovici, Prem R. Menon, David T. Miller
Critical Path Tracing: An Alternative to Fault Simulation. IEEE Des. Test 1 (1) (1984)
Miron Abramovici, Ytzhak H. Levendel, Premachandran R. Menon
A Logic Simulation Machine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 (2) (1983)
Miron Abramovici, Premachandran R. Menon
A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. ITC (1983)
Miron Abramovici, Prem R. Menon, David T. Miller
Critical path tracing - an alternative to fault simulation. DAC (1983)
Miron Abramovici, Melvin A. Breuer
Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis. IEEE Trans. Computers 31 (12) (1982)
Miron Abramovici, Ytzhak H. Levendel, Prem R. Menon
A logic simulation machine. DAC (1982)
Miron Abramovici, Ytzhak H. Levendel, Prem R. Menon
A logic simulation machine. ISCA (1982)
Miron Abramovici
A Hierarchical, Path-Oriented Approach to Fault Diagnosis in Modular Combinational Circuits. IEEE Trans. Computers 31 (7) (1982)
Miron Abramovici
A maximal resolution guided-probe testing algorithm. DAC (1981)
Miron Abramovici, Melvin A. Breuer
Fault diagnosis based on effect-cause analysis: An introduction. DAC (1980)
Miron Abramovici, Melvin A. Breuer
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis. IEEE Trans. Computers 29 (6) (1980)
Miron Abramovici, Melvin A. Breuer
On Redundancy and Fault Detection in Sequential Circuits. IEEE Trans. Computers 28 (11) (1979)
Miron Abramovici, Melvin A. Breuer, K. Kumar
Concurrent fault simulation and functional level modeling. DAC (1977)