Charles E. Stroud

Publication Activity (10 Years)

Years Active: 1986-2011
Publications (10 Years): 0

Publications

Jie Qin, Joseph Cali, Bradley F. Dutton, George J. Starr, Fa Foster Dai, Charles E. Stroud
Selective Spectrum Analysis for Analog Measurements. IEEE Trans. Ind. Electron. 58 (10) (2011)
Charles E. Stroud, Bradley F. Dutton
The First Clock Cycle Is A Real BIST. ESA (2010)
Bradley F. Dutton, Charles E. Stroud
On-Line Single Event Upset Detection and Correction in Field Programmable Gate Array Configuration Memories. Int. J. Comput. Their Appl. 17 (2) (2010)
Brooks R. Garrison, Daniel T. Milton, Charles E. Stroud
Built-in Self-Test for Memory Resources in Virtex-4 Field Programmable Gate Arrays. CATA (2009)
George J. Starr, J. M. Wersinger, Richard Chapman, Lloyd Riggs, Victor P. Nelson, John Klingelhoeffer, Charles E. Stroud
Application of Embedded Systems in Low Earth Orbit for Measurement of Ionospheric Anomalies. ESA (2009)
Bradley F. Dutton, Mustafa Ali, Charles E. Stroud, John Sunwoo
Embedded Processor Based Fault Injection and SEU Emulation for FPGAs. ESA (2009)
Bradley F. Dutton, Charles E. Stroud
Soft Core Embedded Processor Based Built-In Self-Test of FPGAs. DFT (2009)
Mary D. Pulukuri, Charles E. Stroud
On Built-In Self-Test for Adders. J. Electron. Test. 25 (6) (2009)
George J. Starr, Jie Qin, Bradley F. Dutton, Charles E. Stroud, Foster F. Dai, Victor P. Nelson
Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems. DFT (2009)
Bradley F. Dutton, Charles E. Stroud
Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs. ESA (2009)
Bradley F. Dutton, Charles E. Stroud
Single Event Upset Detection and Correction in Virtex-4 and Virtex-5 FPGAs. CATA (2009)
Jie Qin, Charles E. Stroud, Fa Foster Dai
FPGA-Based Analog Functional Measurements for Adaptive Control in Mixed-Signal Systems. IEEE Trans. Ind. Electron. 54 (4) (2007)
John M. Emmert, Charles E. Stroud, Miron Abramovici
Online Fault Tolerance for FPGA Logic Blocks. IEEE Trans. Very Large Scale Integr. Syst. 15 (2) (2007)
Jie Qin, Charles E. Stroud, Foster F. Dai
Noise Figure Measurement Using Mixed-Signal BIST. ISCAS (2007)
Jack R. Smith, Tian Xia, Charles E. Stroud
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults. J. Electron. Test. 22 (3) (2006)
Foster F. Dai, Charles E. Stroud, Dayu Yang
Automatic linearity and frequency response tests with built-in pattern generator and analyzer. IEEE Trans. Very Large Scale Integr. Syst. 14 (6) (2006)
Lee Lerner, Charles E. Stroud
An Architecture for Fail-Silent Operation of FPGAs and Configurable SoCs. ESA (2006)
Daniel T. Milton, Sachin Dhingra, Charles E. Stroud
Embedded Processor Based Built-In Self-Test and Diagnosis of Logic and Memory Resources in FPGAs. ESA (2006)
Charles E. Stroud, Dayu Yang, Foster F. Dai
Analog frequency response measurement in mixed-signal systems. ISCAS (2006)
Srinivas M. Garimella, Charles E. Stroud
Built-In Self-Test and Diagnosis of Multiple Embedded Cores in SoCs. ESA (2005)
Charles E. Stroud, Srinivas M. Garimella, John Sunwoo
On-Chip BIST-Based Diagnosis of Embedded Programmable Logic Cores in System-on-Chip Devices. CATA (2005)
Dayu Yang, Foster F. Dai, Charles E. Stroud
Built-in self-test for automatic analog frequency response measurement. ISCAS (3) (2005)
Charles E. Stroud, John Sunwoo, Srinivas M. Garimella, Jonathan Harris
Built-In Self-Test for System-on-Chip: A Case Study. ITC (2004)
Miron Abramovici, Charles E. Stroud, John M. Emmert
Online BIST and BIST-based diagnosis of FPGA logic blocks. IEEE Trans. Very Large Scale Integr. Syst. 12 (12) (2004)
Foster F. Dai, Charles E. Stroud, Dayu Yang, Shuying Qi
Automatic Linearity (IP3) Test with Built-in Pattern Generator and Analyzer. ITC (2004)
Charles E. Stroud, Keshia N. Leach, Thomas A. Slaughter
BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study. ITC (2003)
Miron Abramovici, Charles E. Stroud
BIST-Based Delay-Fault Testing in FPGAs. J. Electron. Test. 19 (5) (2003)
Charles E. Stroud, Jeremy Nall, Matthew Lashinsky, Miron Abramovici
BIST-Based Diagnosis of FPGA Interconnect. ITC (2002)
Miron Abramovici, Charles E. Stroud
BIST-Based Delay-Fault Testing in FPGAs. IOLTW (2002)
Miron Abramovici, Charles E. Stroud, Marty Emmert
Using embedded FPGAs for SoC yield improvement. DAC (2002)
Miron Abramovici, Charles E. Stroud
BIST-based test and diagnosis of FPGA logic blocks. IEEE Trans. Very Large Scale Integr. Syst. 9 (1) (2001)
John M. Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici
On-Line Fault Tolerance for FPGA Interconnect with Roving STARs. DFT (2001)
Henry Chang, Steve Dollens, Gordon W. Roberts, Charles E. Stroud, Mani Soma, Jacob A. Abraham
Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them? VTS (2001)
Miron Abramovici, Charles E. Stroud, Matthew Lashinsky, Jeremy Nall, John M. Emmert
On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs. IOLTW (2001)
Miron Abramovici, John M. Emmert, Charles E. Stroud
Roving Stars: An Integrated Approach To On-Line Testing, Diagnosis, And Fault Tolerance For Fpgas In Adaptive Computing Systems. Evolvable Hardware (2001)
Charles E. Stroud, James R. Bailey, Johan R. Emmert
A New Method for Testing Re-Programmable PLAs. J. Electron. Test. 16 (6) (2000)
Charles E. Stroud, John M. Emmert, John R. Bailey, Khushru S. Chhor, Dragan Nikolic
Bridging fault extraction from physical design data for manufacturing test development. ITC (2000)
John M. Emmert, Charles E. Stroud, Brandon Skaggs, Miron Abramovici
Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration. FCCM (2000)
John M. Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron Abramovici
Performance Penalty for Fault Tolerance in Roving STARs. FPL (2000)
Miron Abramovici, Charles E. Stroud
DIST-based detection and diagnosis of multiple faults in FPGAs. ITC (2000)
Miron Abramovici, Charles E. Stroud, Brandon Skaggs, John M. Emmert
Improving On-Line BIST-Based Diagnosis for Roving STARs. IOLTW (2000)
Miron Abramovici, Charles E. Stroud, Carter Hamilton, Sajitha Wijesuriya, Vinay Verma
Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications. ITC (1999)
Carter Hamilton, Gretchen Gibson, Sajitha Wijesuriya, Charles E. Stroud
Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access. VTS (1999)
Charles E. Stroud, Sajitha Wijesuriya, Carter Hamilton, Miron Abramovici
Built-in self-test of FPGA interconnect. ITC (1998)
Charles E. Stroud, Joe K. Tannehill Jr.
Applying Built-In Self-Test to Majority Voting Fault Tolerant Circuits. VTS (1998)
Charles E. Stroud, Eric Lee, Miron Abramovici
BIST-Based Diagnostics of FPGA Logic Blocks. ITC (1997)
Charles E. Stroud, M. Ding, S. Seshadri, Ramesh Karri, I. Kim, Subhajit Roy, S. Wu
A Parameterized VHDL Library for On-Line Testing. ITC (1997)
Charles E. Stroud, Eric Lee, Srinivasa Konala, Miron Abramovici
Using ILA Testing for BIST in FPGAs. ITC (1996)
Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). VTS (1996)
Charles E. Stroud, Ping Chen, Srinivasa Konala, Miron Abramovici
Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks. FPGA (1996)
T. Raju Damarla, Wei Su, Gerald T. Michael, Moon J. Chung, Charles E. Stroud
A built-in self test scheme for VLSI. ASP-DAC (1995)
Charles E. Stroud, T. Raju Damarla
Improving the efficiency of error identification via signature analysis. VTS (1995)
T. Raju Damarla, Charles E. Stroud, Avinash Sathaye
Multiple error detection and identification via signature analysis. J. Electron. Test. 7 (3) (1995)
Charles E. Stroud
Reliability of majority voting based VLSI fault-tolerant circuits. IEEE Trans. Very Large Scale Integr. Syst. 2 (4) (1994)
Charles E. Stroud, Ahmed E. Barbour
Testability and test generation for majority voting fault-tolerant circuits. J. Electron. Test. 4 (3) (1993)
Charles E. Stroud
Built-In Self-Test for High-Speed Data-Path Circuitry. ITC (1991)
Charles E. Stroud
Distractions in Design for Testability and Built-Is Self-Test. ITC (1991)
Charles E. Stroud, Ahmed E. Barbour
Parallel Processing and Hardware Acceleration for Synthesis of VLSI Devices from Behavioral Models. ICPP (1) (1990)
Charles E. Stroud, Ahmed E. Barbour
Design for Testability and Test Generation for Static Redundancy System Level Fault-Tolerant Circuits. ITC (1989)
Charles E. Stroud, Ronald R. Munoz, David A. Pierce
Behavioral model synthesis with Cones. IEEE Des. Test 5 (3) (1988)
Charles E. Stroud
Automated BIST for sequential logic synthesis. IEEE Des. Test 5 (6) (1988)
Charles E. Stroud
An Automated BIST Approach for General Sequential Logic Synthesis. DAC (1988)
Sunil K. Jain, Charles E. Stroud
Built-in Self Testing of Embedded Memories. IEEE Des. Test 3 (5) (1986)